Source Junction Research Articles

Three-Terminal Device for Realizing a Voltage-Driven Spin Transistor

We propose a three-terminal device incorporating a magnetic tunnel junction (MTJ) in which the free layer magnetization can be controlled by the separated gate electrode through voltage-induced magnetic anisotropy change—in other words, a voltage-driven spin transistor. We have developed a process for fabricating a three-terminal structure in which the drain and source junctions are connected through the common free layer. The theoretical calculations allow us to discuss how to achieve high-power gain. Because the gate resistance decreases as the junction size decreases, higher power gain can be obtained with a smaller junction size. Power amplification of greater than $10^{\mathrm {4}}$ is achievable if we employ an MTJ with a resistance-area product less than $5~\Omega \cdot \mu \text{m}^{\mathrm {\mathbf {2}}}$ and a junction size less than 50 nm. This three-terminal device structure for realizing a voltage-driven spin transistor represents a promising contribution to the development of high-performance spin transistors.

(Invited) Tunneling FET Technologies Using III-V and Ge Materials

We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/III-V materials. It is found that solid-phase Zn diffusion can realize steep-profile and defect-less p+/n source junctions. We have demonstrated the operation of high Ion/Ioff and low SS planar-type InGaAs tunnel FETs with Zn-diffused source junctions. The small S.S. of 64 mV/dec and large Ion/Ioff ratio over106 has been realized in the planar-type III-V TFETs. It is also shown that tensile strain in Si channels (sSi) combined with the Ge source can enhance the tunneling current because of the reduced effective energy bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high Ion/Ioff ratio over 107 and steep minimum subthreshold slope (SS) of 28 mV/dec.

High Ion/Ioff and low subthreshold slope planar-type InGaAs tunnel field effect transistors with Zn-diffused source junctions

We have demonstrated the operation of high on-off current ratio (Ion/Ioff) and low subthreshold slope planar-type InGaAs tunnel field effect transistors (TFETs) with Zn-diffused source junctions. The solid-phase Zn diffusion process has been shown to form defect-less p+/n source junctions with steep profiles because of the inherent nature of Zn diffusion into InGaAs, which has significantly improved the TFET performance. The devices presented in this paper have exhibited a record low subthreshold slope of 64 mV/dec for planar-type III-V TFETs and a large Ion/Ioff ratio of more than 106 at the same time.

(Invited) Tunneling FET Technologies Using III-V and Ge Materials

Since TFETs based on band-to-band tunneling are expected as ultra-low power devices, development of the optimum materials, structures and fabrication process have been strongly pursued for realizing both low SS of sub-60 mV/dec. and high drain Ion/Ioff ratio at the same time. For this purpose, the reduction in the effective band gap is important for enhancing tunneling current. Thus, we are currently focusing planar-type TFETs using Ge/III-V and their hetero-structures. One of the key issues for TFETs is the formation of the steep and high quality source junctions, which provide both high tunneling current and low off current. In this talk, we address two types of planar TFETs utilizing the Ge/strained Si (sSi) hetero-structure and the InGaAs channels where in-situ doping p+ Ge/sSi and Zn-diffused p+ InGaAs source junctions are employed for realizing steep and defect-less tunneling junction formation. As for the TFET channels, sSi is a realistic material, because of the smaller bandgap. For the TFET sources, pure Ge sources grown on Si are expected to provide higher tunneling current [1, 2], because of the type-II staggered band alignment between Ge and Si [3]. Thus, we have combined the Ge source with strained-SOI channels [4, 5]. The higher Ev edge of the Ge-source and the lower Ec edge of tensile-strained Si result in reduction in the effective band gap, leading to the increase the tunneling probability with maintaining the relatively large Eg of sSi in the drain regions, which can suppress the ambipolar leakage current. It is found that an increase in strain leads to the increase in Ion and the decrease in IG, resulting in high Ion/Ioff ratio because of higher tunneling probability and higher barrier height between insulators and sSi [6]. It is found that PMA temperature strongly affects the electrical properties. The Ion/Ioff ratio is maximized after 400 oC PMA, which amounts to 4.4E7, 2.2E7 and 3.7E7 for the unstrained, 0.8 and 1.1 % strained SOI TFETs, respectively. Also, higher PMA temperature also significantly reduces SS. The unstrained, 0.8 and 1.1 % strained SOI TFETs after 400 oC PMA yield SSmin of 55, 49 and 29 mV/dec, respectively, at room temperature. This better performance with higher PMA temperature is attributed to lower Dit at the Si MOS interfaces [7]. Also, the ID-VG characteristics are almost independent of temperature, meaning that any defect-related currents are effectively suppressed and the tunneling current dominates over the operation of the devices. InGaAs is a promising material of TFETs, because of the high tunneling probability due to the narrow and direct bandgap. Here, formation of the source junctions with defect-free and steep impurity profiles is mandatory for InGaAs TFETs. From this viewpoint, we have introduced solid- phase Zn diffusion in InGaAs through utilizing the inherent diffusion property of Zn in InGaAs creating defect-less extremely-steep profiles [8]. It is found from SIMS that the steepness of the Zn profiles is less than 3.5 nm/dec. This result is consistent with the model that diffusion constant of Zn in InGaAs is proportional to the square of the Zn concentration [9], ensuring the automatic realization of the steep impurity profile. The devices exhibited the small SSmin of 64 mV/dec. and the large Ion/Ioff ratio over 1E6 at the same time as the planar-type III-V TFETs with EOT of 1.3 nm. We have also found almost no temperature dependence of ID, confirming the dominance of band-to-band tunneling on the present devices. These results show the superior p+/n junctions formed by Zn solid phase diffusion in InGaAs. In conclusion, the enhancement of tunneling probability by utilizing III-V/Ge materials is quite effective in improving the performance of TFETs. Superior source junction formation and MOS interface control technologies are key factors to realize TFETs using III-V/Ge. This work was partially supported by JST-CREST, and JSPS Core-to-Core Program, A. Advanced Research Networks. We would be grateful to Drs. H. Yamada, O. Ichikawa, T. Osada and M. Hata in Sumitomo Chemical Corporation for continuous support on III-V epi substrates and SOITECH for providing strained SOI substrates.

Flexible semi-around gate silicon nanowire tunnel transistors with a sub-kT/q switch

Tunnel field-effect transistors (TFETs) with a subthreshold swing (SS) < 60 mV/dec are expected to be active devices in low-power flexible systems, potentially lowering operational voltage by virtue of steep switching behavior via band-to-band tunneling. In silicon (Si) channel materials, however, it still remains a challenge to obtain SS smaller than 60 mV/dec. In this study, we experimentally demonstrate the sub-60 mV/dec operation of a flexible semi-around gate TFET on a plastic substrate using Si nanowires (SiNWs) as the channel material. With the combined advantages of selectively thinned SiNW channels (width ∼ 15 nm and height ∼ 40 nm) and high-κ (Al2O3 ∼ 7 nm) gate dielectric, in conjunction with an abrupt degenerate source junction, the device with a channel length of ∼500 nm exhibits a minimal SS of ∼42 mV/dec at room temperature. Moreover, mechanical bendability of the device indicates that it has stable and good fatigue properties, providing an important step towards the realization of steep-slope switches for low-power and energy-efficient flexible electronics.

Analytically Modeling the Asymmetric Double Gate Tunnel FET

This paper proposes an analytical model for the asymmetric double-gate (ADG) TFET operation. Two-dimensional Poisson equation is solved based on the depletion approximation [1,2]. The two-dimensional potential function is given by appropriate boundary conditions. Internal electric field is calculated from the potential model and tunnel current is numerically calculated using the Kane’s tunnel current generation model [3,4]. We used the commercial TCAD simulator in order to examine the analytical model [5]. Schematic of ADG-TFET device structure is shown in Fig. 1. It is assumed that p-type source and n-type drain regions are highly doped. Channel region is a p-type with the doping level of Na . tox denotes the gate oxide thickness and tsi denotes the semiconductor film thickness. Hereafter, we call the top gate “front gate” and the bottom gate “back gate”. Potential profile of the channel region is derived from the following two-dimensional Poisson equation based on the depletion approximation. Equation (1) where q denotes the elemental charge and εsi denotes the permittivity of semiconductor. Here, we assume the following potential function with the cubic function of coordinate y [1]. Equation (2) where four factors a(x), b(x), c(x), and d(x) are functions of coordinate x. We introduce the following boundary conditions for the potential in solving eq. (1). Equation (3) where ψf(x) and ψb(x) stand for front and back surface potentials at y=0 and y=t si, respectively. Vfg,fb and Vbg,fb are the front-gate and the back-gate flat-band voltages, respectively. Vfg and Vbg are the front- and back-gate voltages, respectively. εox is the permittivity of gate insulator. Drain current of ADG TFET is numerically calculated by integrating carriers tunneling from the valence band of the source region to the conduction band of the channel region. We can calculate the drain current (IDS ) using the carrier generation rate (G) due to the band-to-band tunnel process. Equation (4) where we use the Kane’s model for the carrier generation rate (G) [3,4]. Equation (5) where |E| (=(Ex 2+Ey 2)1/2 ) is the electric field strength, A and B are constants given byEquation (Si) Equation (Ge) We perform the TCAD simulation [5] in order to examine the validity of the analytical model. In device simulations for Si-based TFETs, we assume the gate material with the work function of 4.1 eV for the front- and the back-gate electrodes. Figure 2 shows the calculated potential profiles at y=0nm, 2.5nm, and 5.0nm for tsi =10nm. Using the potential function revealed in Fig. 2, local electric field values are calculated along with the x direction and the y direction separately. The potential function analytically given and resulting electric fields successfully reproduced those given by TCAD simulations (not shown here). We found a slight difference of potential profile near the surface around the source junction for a relatively low-doping source region because of the depletion in the source region [6]. We also calculated drain current characteristics. Figure 3 demonstrates ID-Vfg characteristics for tsi =10nm and 20nm, where the condition of Lg >2ts is satisfied. In Fig. 5, the model basically reproduces the TCAD result. On the other hand, the model doesn’t well reproduce TCAD-based ID-Vgf characteristics for tsi =30nm and 100nm (not shown here), where Lg <2tsi . This difference stems from the linear approximation of the in-depth electric field in the model. As the condition of Lg >2tsi is important in the future, this is not a crucial issue of the model. In addition, we confirmed the model proposed here is available for Ge-based TFET (not shown here).

Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism

The goal of this work is to study the analog performance of tunnel field effect transistors (TFETs) and its susceptibility to temperature variation and to different dominant transport mechanisms. The experimental input characteristic of nanowire TFETs with different source compositions (100% Si and Si1−xGex) has been presented, leading to the extraction of the Activation Energy for each bias condition. These first results have been connected to the prevailing transport mechanism for each configuration, namely band-to-band tunneling (BTBT) or trap assisted tunneling (TAT). Afterward, this work analyzes the analog behavior, with the intrinsic voltage gain calculated in terms of Early voltage, transistor efficiency, transconductance and output conductance. Comparing the results for devices with different source compositions, it is interesting to note how the analog trends vary depending on the source characteristics and the prevailing transport mechanisms. This behavior results in a different suitability analysis depending on the working temperature. In other words, devices with full-Silicon source and non-abrupt junction profile present the worst intrinsic voltage gain at room temperature, but the best results for high temperatures. This was possible since, among the 4 studied devices, this configuration was the only one with a positive intrinsic voltage gain dependence on the temperature variation.

Modeling the Impact of Multi-Fingering Microwave MOSFETs on the Source and Drain Resistances

Modern MOSFETs operated at high frequencies are designed and fabricated using a multi-fingered structure to enhance performance, especially to reduce gate resistance. However, even though the layout-dependent effect of other parasitics, such as that related to the source and drain resistances, is becoming more important, it has not been extensively investigated at high frequencies. In this paper, source and drain resistances are experimentally determined and analyzed for several microwave MOSFETs to characterize their corresponding dependence on the layout. This allows for the quantification and modeling of the impact of the device's geometry on its parasitic extrinsic parameters. Physically based closed-form equations are proposed here to accurately represent S-parameters of MOSFETs operating at microwave frequencies with layouts considering different numbers of gate fingers, and grouping devices in cells with multiple source and drain junctions. The proposed models are compatible with SPICE-like circuit simulators, and an excellent model-experiment correlation is obtained when using the proposed scalable equations to represent different geometry MOSFETs up to 60 GHz.

Memory effect in a ferroelectric single-electron transistor: Violation of conductance periodicity in the gate voltage

The fundamental property of most single-electron devices with quasicontinuous quasiparticle spectrum on the island is the periodicity of their transport characteristics in the gate voltage. This property is robust even with respect to placing the ferroelectric insulators in the source and drain tunnel junctions. We show that placing the ferroelectric inside the gate capacitance breaks this periodicity. The current-voltage characteristics of this SET strongly depends on the ferroelectric polarization and shows the giant memory-effect even for negligible ferroelectric hysteresis making this device promising for memory applications.

Electrically-activated source extension graphene nanoribbon field effect transistor: Novel attributes and design considerations for suppressing short channel effects

In this paper a double gate graphene nanoribbon field effect transistor with electrically-activated source extension is proposed. Source region of the proposed structure includes two sections, an electrically-activated extension and a doped section. The electrically extension, which is located between doped source section and gate region, is biased independent of the gate to form a virtual extension for source. The electrically-activated extension creates a step in potential profile which increases the horizontal distance between conduction and valance bands at channel to source junction. This step reduces the probability of band to band tunneling, lowers the leakage current and improves drain induced barrier lowering. The devices have been simulated based on self consistent solution of Poisson and Schrodinger equations within non-equilibrium Green’s function formalism. In addition, the effects of the edge and third nearest neighbor are included for more accurate outcomes. Simulations show that the proposed structure is a more reliable device because of its higher ON/Off current ratio, shorter delay time, and smaller power delay product beside lower subthreshold swing than conventional graphene nanoribbon field effect transistor.

Dissipative planar gravitational collapse in f(G) gravity

This paper is devoted to analyze the dynamics of plane symmetric gravitational collapse as well as energy density inhomogeneity in f(G) gravity. The field equations are constructed for dissipative isotropic source and Darmois junction conditions are used to discuss the process of collapse. We use Misner–Sharp mechanism to develop dynamical equation and couple it with transport equation to explore the impact of gravitational force on the collapsing rate. For constant f(G) model, we conclude that the rate of collapse slows down. Finally, we discuss the relationship between the Weyl tensor and physical quantities.

Source Doping Profile Design for Si and Ge Tunnel FET

The source junction doping profile design for Si and Ge tunnel FET (TFET) is discussed and compared in this paper. By using Sentaurus TCAD tools with calibrated dynamic non-local band-to-band tunneling and non-local trap-assisted-tunneling models, it is shown that when Si TFET’s source doping gradient increases from 1.5 to 15 nm/dec, due to the gradual band bending and lower electric field at tunnel junction, average subthreshold slope (SS) increases from 38 to 64 mV/dec, onset voltage increases by 0.1 V and ON-current decreases by almost one decade. Although Ge TFET has larger tunneling electric field, the doping profile impact on SS is more severe than that of Si TFET. The design margin for doping profile under different gate length, gate oxide thickness and source-gate overlap is also discussed. Results show that for short channel Si TFETs, doping profile design margin for SS below 60mV/dec decreases as gate length shortens. For short channel Si TFETs design, the process requirement of abrupt source doping profile can be relaxed if thin gate oxide and a small underlap at the source junction are employed, and more stringent process control is required for Ge TFETs.

Design Guidelines of In0.53Ga0.47As and Si Tunneling Field-Effect Transistors

In this paper, the impacts of the source doping profile, effective oxide thickness (EOT), gate alignment, and trap density at the source junction on key characteristics of In0.53Ga0.47As- and Si-based tunneling field-effect transistors (TFETs) were comprehensively analyzed through Sentaurus simulations with calibrated models, which can provide some guidelines for device and process design. The simulations show that the EOT and the gate alignment should be carefully designed and controlled for both Si and In0.53Ga0.47As TFETs fabrication. The EOT needs a tighter control in In0.53Ga0.47As TFETs, a suitable gate-source underlap can optimize the performance of device considering a non-ideal source doping profile. Moreover, the trap density at the source junction plays more significant impacts in In0.53Ga0.47As TFETs than Si TFETs.

Source-side injection single-polysilicon split-gate flash memory

The source-side injection single-polysilicon split-gate NOR (S4-NOR) flash memory is proposed for embedded applications. For the S4-NOR cell, the access and floating gates are patterned on the channel between the source and drain junctions with a gap length of 55 nm using conventional photolithography technology, and the floating gate is capacitively coupled to an n-well memory gate. This technology can improve the compatibility with a single-polysilicon CMOS logic process. The memory cell is programmed within 5 µs with a low drain current of 10 µA, and its program efficiency is insensitive to process parameters except gap length, which are suitable for embedded memories from the process control viewpoint in addition to low power consumption. Good reliability is also realized without the effect of gap oxide leakage. Furthermore, the performance and reliability of the S4-NOR cell can be improved by scaling the logic process without using any special process.

Power gain improvement for single-electron transistors

In this paper, a novel approach for investigating the single-electron transistors (SET’s) power gain functionality which is one of the most important features of active devices related with operation speed performance is proposed. Moreover, an evaluating method is also introduced to improve the SET power gain due to the influence of junction thickness. It is found that source junction thickness is the key factor affecting the power gain. This important finding is illustrated by taking into account the physical parameters of a sample fabricated SET. According to proposed model, power gain can be improved by a remarkable amount of 39 dB at frequencies up to THz regime by reducing 1.25 nm in source junction thickness.

Germanium–Tin P-Channel Tunneling Field-Effect Transistor: Device Design and Technology Demonstration

We report the demonstration of germanium-tin (GeSn) p-channel tunneling field-effect transistor (p-TFET) with good device performance in terms of on-state current (Ion). With the incorporation of Sn, the conduction band minima at Γ-point of GeSn alloy shift down, increasing the direct band-to-band tunneling (BTBT) generation rate at the source-channel tunneling junction in TFET. In addition, n-type dopant activation temperature of below 400 °C can be used in GeSn, which is much lower than that in Ge (700 °C). Therefore, n-type dopant diffusion in GeSn is suppressed leading to an abrupt n+ tunneling junction that is favorable for the source junction of a p-TFET. Lateral Ge0.958Sn0.042 p-TFETs were fabricated and high Ion of 29 μA/μm at VGS = VDS = -2 V and 4.34 μA/μm at VGS = VDS = -1 V is achieved.

The roles of grain boundary dislocations and disclinations in the nucleation of {1 0 [formula omitted] 2} twinning

Consider a magnesium bicrystal created from two single crystal lattices referred to as black and white. The bicrystal abuts a basal plane of the black crystal with a first-order prismatic plane of the white crystal. At zero stress, the boundary relaxes by developing coherent terraces, while two types of disconnection dipoles and a misfit dislocation above each dipole nucleate, in combination, to remove the attendant long-range elastic strains and maximize local coherency. When the bicrystal is stretched normal to its semicoherent interface, stress motivates the misfit dislocation at the far side of the boundary to glide and annihilate at the triple point. The removal of this bounding misfit dislocation allows the positive step of the disconnection dipole to conservatively move away. The negative step of this dipole, however, remains sessile at the grain boundary as it cannot glide conservatively. This sessile step facilitates nucleation of a new disconnection dipole. The first process of disconnection dipole widening then repeats, and the new residual negative step coalesces with the first one to form a novel disconnection of double step height. The whole process cycles once more, and two of these double-height disconnections pile-up at the boundary. The pile-up quickly relaxes into a coherent boundary along the {101¯2} plane; a {101¯2} twin facet thus nucleates, and a disclination dipole arises to bound the twin facet at the two junctions. Soon thereafter, the lower disclination, at the opposite side from where the misfit was removed, begins emitting twinning disconnections toward the upper disclination. These twinning disconnections caused their source junction to recede in favor of an overwhelming lengthening of the twin facet. All twinning disconnections end up moving through the upper disclination, thereby undergoing a dislocation transformation event. The new transformed disconnection glides freely along the remaining basal-prismatic boundary segment, and enables this boundary to be dragged with the propagating twin facet. This steady stage proceeds until the entire bicrystal transforms in to a single twinned crystal. This paper examines the fundamentals of these twin nucleation mechanisms at the grain boundary on the basis of the interfacial defect theory advanced by Pond and co-workers [1,2]. It introduces an important twin nucleation mechanism with dynamics of twin faceting in relation to an important asymmetric low-energy boundary in hexagonal close-packed materials.

Investigation on the Corner Effect of &lt;I&gt;L&lt;/I&gt;-Shaped Tunneling Field-Effect Transistors and Their Fabrication Method

In this work, electrical characteristics of L-shaped tunneling field-effect transistors (TFETs) have been studied and optimized by a commercial device simulator: Synopsys Sentaurus. Unlike our previous study performed by using Silvaco Atlas, there exists a kink phenomenon in a transfer curve which degrades the subthreshold swing (SS) and on-current (lon) of TFETs. According to simulation results, the kink results from abrupt source doping. Rounding the source junction edge with gradual doping profile is helpful to alleviate it. Based on those results, a novel fabrication flow has been proposed to suppress the kink effect induced by source corners. It is predicted that the performance of L-shaped TFETs is improved in terms of SS and Ion under the optimized process condition. Furthremore, the effect of high-k gate dielectric and narrow band gap material on device performance has been examined. Using 2-nm-thick HfO2 for gate dielectric and Si0.7Ge0.3 for intrinsic tunneling region, gate controllability to the channel and tunneling probability have been enhanced. As a result, its threshold voltage (Vth), SS and Ion have been improved by 0.13 V, 16 mV/dec, and 3.62 microA/microm, respectively.

Dopant-Free CMOS on SOI: Multi-Gate Si-Nanowire Transistors for Logic and Memory Applications

In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The fabricated MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure.

Junction Engineering of 1T-DRAMs

One-transistor dynamic random access memories (DRAMs) (1T-DRAMs) are considered a promising candidate to overcome the limits of scalability of conventional one-transistor/one-capacitor DRAMs. Robust and reproducible operation has been demonstrated by experiments in MOSFET devices with a gate length ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> ) down to ~50 nm, which prevents their use in future technological nodes. The main factors limiting the retention time of 1T-DRAMs are the Shockley-Read-Hall recombination in the channel and the band-to-band tunneling between channel and source/drain junctions, both enhanced by the relatively high field at both junctions. In this letter, we show through statistical device simulations on a template double-gate MOSFET that, by introducing an underlap of ~16 nm between the drain (source) junction and the gate, it is possible to reduce both the electric field at the junction and the impact of process variability, achieving 1T-DRAMs with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> = 10 nm with a retention time in excess of 100 ms. We also show that field plates at the source and drain contacts do not provide additional advantages and that the junctionless transistor operation as 1T-DRAM is totally undermined by the impact of random dopants.