Abstract
In this paper, the impacts of the source doping profile, effective oxide thickness (EOT), gate alignment, and trap density at the source junction on key characteristics of In0.53Ga0.47As- and Si-based tunneling field-effect transistors (TFETs) were comprehensively analyzed through Sentaurus simulations with calibrated models, which can provide some guidelines for device and process design. The simulations show that the EOT and the gate alignment should be carefully designed and controlled for both Si and In0.53Ga0.47As TFETs fabrication. The EOT needs a tighter control in In0.53Ga0.47As TFETs, a suitable gate-source underlap can optimize the performance of device considering a non-ideal source doping profile. Moreover, the trap density at the source junction plays more significant impacts in In0.53Ga0.47As TFETs than Si TFETs.
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