Source Doping Profile Design for Si and Ge Tunnel FET

Abstract

The source junction doping profile design for Si and Ge tunnel FET (TFET) is discussed and compared in this paper. By using Sentaurus TCAD tools with calibrated dynamic non-local band-to-band tunneling and non-local trap-assisted-tunneling models, it is shown that when Si TFET’s source doping gradient increases from 1.5 to 15 nm/dec, due to the gradual band bending and lower electric field at tunnel junction, average subthreshold slope (SS) increases from 38 to 64 mV/dec, onset voltage increases by 0.1 V and ON-current decreases by almost one decade. Although Ge TFET has larger tunneling electric field, the doping profile impact on SS is more severe than that of Si TFET. The design margin for doping profile under different gate length, gate oxide thickness and source-gate overlap is also discussed. Results show that for short channel Si TFETs, doping profile design margin for SS below 60mV/dec decreases as gate length shortens. For short channel Si TFETs design, the process requirement of abrupt source doping profile can be relaxed if thin gate oxide and a small underlap at the source junction are employed, and more stringent process control is required for Ge TFETs.