Source Junction Research Articles

Experimental and numerical study of structural parameters on the heat transfer performance of submerged cooling system

Immersion direct contact cooling effectively transfers heat from electronic components to a cooling solution without additional thermal resistance, due to its high energy density, low power consumption, system simplicity, and integrated thermal management for electronic devices. Current scholarly research on immersed structures predominantly focuses on surface temperature effects, with a scant investigation into internal flow and temperature field distributions concerning boundary layers. This study addresses structural optimization in immersion cooling systems, employing experimental and simulation methods to elucidate the thermal mechanisms by which structural optimization impacts the performance of chip immersion cooling systems. The research examines the impact of panel spacing and liquid level height on the thickness of velocity and thermal boundary layers, as well as the combined effects of natural and forced convection under three distinct cooling modes. Analysis reveals that heat pipe immersion cooling can reduce the heat source junction temperature to 40.7 °C under a 60 W power dissipation, a 47.2 % decrease from the bare heat source temperature. Reducing panel spacing disrupts the thermal boundary, enhancing forced convection and lowering the junction temperature by up to 10.1 % (6.5 °C). As liquid level height increases, the junction temperature initially decreases and then rises, with an optimal height of 175 mm for the best overall heat transfer effect. At low flow velocities (0.04 m/s), the vertical buoyancy-induced flow velocity at the heat source surface (24.2 × 10-6 m/s) exceeds the horizontal forced convection velocity (0.78 × 10-6 m/s), indicating that buoyancy changes due to density differences are significant and must be considered.

Electrical characteristics assessment and noise analysis of pocket-doped multi source T-shaped gate tunnel FET

A detailed analysis of a novel multi-source T-shaped gate Tunnel FET (MS-TTFET) is presented in this study in order to address the main issues with conventional TFETs. Due to its exceptionally low off-state current (IOFF) and remarkable sub-threshold properties, the tunnel field effect transistor has received a great deal of interest for low standby power applications. The MSR's integration into the SOI platform increases the device's on current, which increases the effective tunnelling area in the middle of the source-channel junctions. An isolator oxide has been added to prevent the source and drain regions from being directly coupled. A SiGe pocket has been suggested at the source and channel junction; silicon-germanium, a low bandgap material which enhances the tunnelling of charge carriers. A T-shaped gate can increase the effectiveness of the tunnel junction in order to limit the lower value of the leakage current. The multi-source regions of the T-shaped gate tunnel field effect transistor can boost the on-state current (ION) by improving tunnel junction areas. The device's ION/IOFF ratio, which is 1013 for our suggested construction, is the standard measure of merit for any device. It is possible to achieve an increased ON current of the order of 10−5 A/μm with a negligible subthreshold swing (SS) of 42 mV/decade. Moreover, the effect of low frequency flicker noise on the device behavior has been investigated.

Effects of Material and Doping Profile Engineering of Source Junction on Line Tunneling FET Operations

Effects of Material and Doping Profile Engineering of Source Junction on Line Tunneling FET Operations

Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

Effects of Polycrystalline Silicon Plug Defect on DRAM Characteristics

This study first demonstrates the effect of polycrystalline silicon plug defects, including voids and seams in dynamic random access memory (DRAM) storage node contact (SNC), on product characteristics. The defect portion of SNC has increased continually due to a reduction in the contact area, an increase in the doping concentration, and low-pressure chemical vapor deposition (LPCVD) process limitations. We validate the effect through defect removal experiments. Numerous methods, such as the cyclic deposition/etch/deposition process of silicon, ion implantation, and laser annealing, are used. The experiments are successful without any side effects using a high-density laser annealing process. The contact resistance of the sample-removed polysilicon defect decreases by 59% and the cell drain current increases by 6%. In addition, the overlap capacitance of the drain node and cell gate edge (Cov) variations by the SNC dopant diffusion forming the source and drain junction of the cell transistor is improved by 6%. Finally, we conduct the row precharge delay from the last data-in (tRDL) time delay reliability test using mass production test technology and it was confirmed that the contact area standard that satisfies the product quality target is improved by 10%. We propose a new direction for polycrystalline silicon SNC development for a sub-20-nm DRAM device based on this experiment.

The effect of gate geometric effect and polysilicon doping on the performance of scaled NMOS

Insufficiently high doping in polysilicon gates of metal oxide semiconductor field effect transistor (MOSFET) becomes unavoidable due to the demands for low-energy ion implantation and limited annealing conditions to achieve ultra-shallow source and drain junctions. This results in the poly-depletion effect for ultra-thin MOSFET, loss of current drive and shift in the threshold voltage. This problem gets intense when the device is further scaled down for the gate length and thickness of gate oxide. Hence, our current work focuses on the effect of gate geometrical effect and polysilicon gate doping on scaled n-channel MOSFET(NMOS) performance. The NMOS device was constructed using TCAD ATLAS tools from SILVACO software. Six different gate lengths of 0.6 μm, 0.4 μm, 0.2 μm, 60 nm, 40 nm and 20 nm were set, and the n-type doping concentration in the polysilicon gate was varied to 1× 1018, 1× 1020 and 1 × 1021 cm-3 respectively to see their effect on the NMOS I-V and C-V performances. The findings showed that as the gate length is scaled down, the drain current increases, and as the concentration of the polysilicon doping increases, the value of the threshold voltage, VTH decreases. Based on the simulation and data collected, it can be concluded that the optimum concentration of polysilicon doping that can reduce the poly-depletion effect is 1 × 1021 cm-3, and the optimum gate length that can be used to overcome the problem is 20 nm.

High performance nanoscale SOI MOSFET with enhanced gate control

A nanoscale SOI MOSFET structure with enhanced gate control is provided in this article. The gate is positioned in the silicon region's center and surrounded by insulating HfO2 and SiO2. Using this structure, we attempt to enhance the gate control over the channel. Furthermore, the source connection is positioned horizontally within the silicon region to generate an electric field caused by the potential difference between the gate and the source junction in the channel region. In fact, in addition to enhanced control of the gate over the channel, the idea of utilizing gate and source connections within the silicon region has led to the maximum electron temperature shifting from the channel to the drain region. Also, generating an undoped silicon region has been feasible to lower the lattice temperature. In addition, the electrical characteristics of the proposed MOSFET in both DC and AC states will be improved. The electrical features such as effective mobility, hot electron effect, electric field, and self-heating effect have been improved. The proposed structure is designed for RF applications and is studied in the 1 MHz to 500 GHz range. The frequency characteristics of the proposed structure, like the gate-source and gate-drain capacitors, S parameters, maximum unilateral power gain, transducer power gain, minimum noise figure, and noise conductance have also been enhanced.

New insights into the effect of spatially distributed polarization in ferroelectric FET on content addressable memory operation for machine learning applications

In this work, the impacts of spatially distributed polarization in Ferroelectric FET (FeFET) on the performance of content addressable memory (CAM) circuits are investigated. It is found that for CAM operation with large pre-charging voltage in the match line, the storage state in FeFET will be changed with the lower polarization near drain side, resulting in the strong non-uniformity of polarization along the channel direction. The lateral electric field generated by source and drain junction due to short channel effect will further exacerbate this effect. It is further shown that this distributed polarization effect may lead to significant circuit performance difference compared with uniform polarization situation, and may further degrade the search accuracy especially for multi-bit CAM. This work indicates the crucial role of polarization distribution effect in the device-circuit co-optimization of FeFET.

A new pocket-doped NCFET for low power applications: Impact of ferroelectric and oxide thickness on its performance

Negative capacitance field-effect transistor (NCFET) is a potential device that has exhibited an immense prospective to outplace conventional FETs because of their steep switching characteristics driven by ferroelectric gate stack. The negative capacitance in ferroelectrics yields a voltage step-up action that curtails the sub-threshold swing (SS) below 60 mV/decade. In this work, a device based on single gate NCFET (SG-NCFET) and a highly doped double pocket double gate (HDDP-DG-NCFET) with n++ pocket at the edge of source and drain channel junction are proposed to investigate the impact of the morphological modification on electrical parameters of NCFET. In addition, the effect of incorporating pocket in HfO2 based single gate and double gate NCFET is investigated that delivers steep SS and enhances the switching ratio. The device architecture is designed systematically to boost ION/IOFF ratio by optimizing the pocket thickness and ferroelectric parameters. Various scaling parameters are optimized to achieve an OFF current of 1.9 × 10−11 A/μm, 2.65 × 10−13 A/μm, ON-OFF current ratio of 108, 1010 and SS of 36.2 mV/decade, 25.5 mV/decade for SG-NCFET and HDDP-DG-NCFET, respectively. Finally, the proposed NCFET characteristics are compared to those of prevailing NCFET designs and the HDDP-DG-NCFET design emerges out to be a better solution for low-power applications.

Experimental investigation on the smoke back-layering length in a branched tunnel fire considering different longitudinal ventilations and fire locations

Most previous works concentrated on the smoke back-layering length in traditional single tunnel fires, whereas very few studies have been performed related to the smoke back-layering length(L) in a branched tunnel fire. In the present paper, a series of fire tests were performed in a 1/10 scale branched tunnel to investigate L under various longitudinal ventilation velocities (v), heat source locations(d) (the distance between the heat source centerline and junction) and heat release rate (HRR). The smoke back-layering length and smoke temperature for various conditions are obtained and analyzed. The results are summarized as follows: With longitudinal ventilation velocity increasing to large enough, the smoke back-layering phenomenon will be observed and the maximum smoke temperature tends to deflect downstream. The larger the v and the farther the heat source is to the intersection, the smaller the L is. The dimensionless smoke back-layering length L/H is proportional to gHQ˙/ρ0cpT0v3A, which is consistent with Thomas's work. Whereas, due to that the smoke will split in intersection of branched tunnel, the proportional coefficient increases from 0.467 to 0.754, which is less than that in traditional single tunnels in previous work. Moreover, a revised relation is proposed to describe the smoke back-layering length in branched tunnel fires considering the longitudinal ventilation and fire location.

Inkjet-Printing-Based Density Profile Engineering of Single-Walled Carbon Nanotube Networks for Conformable High-On/Off-Performance Thin-Film Transistors.

Random networks of single-walled carbon nanotubes (SWCNTs) offer new-form-factor electronics such as transparent, flexible, and intrinsically stretchable devices. However, the long-standing trade-off between carrier mobility and on/off ratio due to the coexistence of metallic and semiconducting nanotubes has limited the performance of SWCNT-random-network-based thin-film transistors (SWCNT TFTs), hindering their practical circuit-level applications. Methods for high-purity separation between metallic and semiconducting nanotubes have been proposed, but they require high cost and energy and are vulnerable to contamination and nanotube shortening, leading to performance degradation. Alternatively, additional structures have been proposed to reduce the off-state current, but they still compromise carrier mobility and suffer from inevitable expansion in device dimensions. Here, we propose a density-modulated SWCNT network using an inkjet-printing method as a facile approach that can achieve superior carrier mobility and a high on/off ratio simultaneously. By exploiting picoliter-scale drops on demand, we form a low-density channel network near the source and drain junctions and a high-density network at the middle of the channel. The modulated density profile forms a large band gap near the source and drain junctions that efficiently blocks electron injection under the reverse bias and a narrow band gap at the high-density area that facilitates the hole transport under the on-state bias. As a result, the density-modulated SWCNT TFTs show both high carrier mobility (27.02 cm2 V-1 s-1) and a high on/off ratio (>106). We also demonstrate all-inkjet-printed flexible inverter circuits whose gain is doubled by the density-modulated SWCNT TFTs, highlighting the feasibility of our approach for realizing high-performance flexible and conformable electronics.

The Effect of Grain Boundary on Electrical Characteristics in the Source and Drain Regions of Polycrystalline Silicon Based in One Transistor Dynamic Random Access Memory.

In this paper, we present a capacitorless one transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) double gate MOSFET with grain boundaries (GBs). Several studies have been conducted to implement 1T-DRAM using poly-Si. This is because poly-Si has the advantage of low-cost fabrication and can be stacked. However, poly-Si has GBs, which can adversely affect semiconductor device. So far, related studies on poly-Si-based 1T-DRAM have only focused on GBs present in the channel domain. Hence, in this study, we analyzed the transfer and memory characteristics when a GB is present in the source and drain regions. As a result, we found that in the center of the depletion region in the source and channel junction, where the effect of GB was most significant, sensing margins decreased the most from 0.88 to 0.29 μA/μm, and retention time (RT) decreased from 85 ms to 47 μs. In addition, we found that at the center of the depletion region in the drain and channel junction, where the effect of GBs was most significant in the drain region, RT decreased the most from 85 ms to 52 μs.

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory.

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory's data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, "0" state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET

The energy deposition and electrothermal behavior of SiC metal–oxide–semiconductor field-effect transistor (MOSFET) under heavy ion radiation are investigated based on Monte Carlo method and TCAD numerical simulation. The Monte Carlo simulation results show that the density of heavy ion-induced energy deposition is the largest in the center of the heavy ion track. The time for energy deposition in SiC is on the order of picoseconds. The TCAD is used to simulate the single event burnout (SEB) sensitivity of SiC MOSFET at four representative incident positions and four incident depths. When heavy ions strike vertically from SiC MOSFET source electrode, the SiC MOSFET has the shortest SEB time and the lowest SEB voltage with respect to direct strike from the epitaxial layer, strike from the channel, and strike from the body diode region. High current and strong electric field simultaneously appear in the local area of SiC MOSFET, resulting in excessive power dissipation, further leading to excessive high lattice temperature. The gate–source junction area and the substrate–epitaxial layer junction area are both the regions where the SiC lattice temperature first reaches the SEB critical temperature. In the SEB simulation of SiC MOSFET at different incident depths, when the incident depth does not exceed the device’s epitaxial layer, the heavy-ion-induced charge deposition is not enough to make lattice temperature reach the SEB critical temperature.

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM.

A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

More physical understanding of current characteristics of tunneling field-effect transistor leveraged by gate positions and properties through dual-gate and gate-all-around structuring

In this work, a tunneling field-effect transistor (TFET) in the structure that can maximize the electrostatic effects in determining its electrical performances is optimally designed and characterized. The featured device structure includes gate-all-around (GAA) channel and dual gates (DuGs) identified as control gate (CG) and adjust gate (AG), respectively. Not along with the design tasks, more fundamental studies on the effects of respective gates on device performances are sought. It has been found that the relatively different vicinities of the DuGs to source and drain junctions have differentiable dominances in controlling the primary direct-current (DC) parameters of the TFET including threshold voltage (Vth), on-state current (Ion), subthreshold swing (S), and on/off current ratio (Ion/Ioff). For the systematic study, four different cases have been presumably schemed giving the degree of freedom in gate workfunctions and inter-gate connectivity. It has been found that the CG at the source side more effectively modulates Vth, Ioff, and S, while the AG at the drain side shows the higher controllability over Ion and Ion/Ioff of the TFET. An optimally designed GAA DuG demonstrated Ion/Ioff > 1011 along with a small S of 14.6 mV/dec, which supports the strong potential of the GAA DuG TFET in the low-power applications.

Analytical modeling and simulation analysis of T-shaped III-V heterojunction vertical T-FET

Abstract In this paper, we have developed a new 2D compact analytical model for surface potential and drain current for III-V group heterojunction of T-shaped Vertical Tunneling FET with inherited properties of dual modulation effect. The device's surface potential is determined from the compact model, which is the most significant consideration for defining device current characteristics. There have been numerous efforts to predict the electrical characteristics of In0.53Ga0.47As as a heterojunction and to discuss the method of device improvement as a function of mole-fraction, gate-drain biasing potential, gate metal work-function. To determine the tunneling width, the dual modulation effect is used to regulate the biasing voltage at both the source and drain junction. A 2-D Poisson equation is solved for the proposed model by using parabolic approximation method with constant electric field which are used to determine the effect of In0.53Ga0.47As as a comparison to Silicon and SiGe material device. Moreover, a new expression of channel surface potential is derived that can forecast the effect of drain and gate biasing. The derived model results validation is carried out by the comparison with the results obtained by TCAD simulation.

Low‐Power Complementary Inverter with Negative Capacitance 2D Semiconductor Transistors

AbstractA fundamental limit for the supply voltage of conventional field‐effect transistors is the long high‐energy tail of the Boltzmann distribution of the carrier population at the source junction, which requires a gate voltage at least 60 mV to change one decade of current. Here 2D semiconductors are adopted as channel materials and hafnium zirconium oxide (HZO) as negative capacitance (NC) gate stack to realize low‐power complementary logic inverter. With HZO/Al2O3 NC gate stack, the 2D semiconductor field‐effect transistor (FET) shows an average subthreshold slope less than Boltzmann limit (as low as 18 mV dec−1) at room temperature for both forward and reverse gate voltage sweeps, which allows to reach the same ON‐state current at a lower Vdd without increasing the OFF‐state current. The drain current can be modulated by 5 × 104 within 220 mV, still exhibiting average SS below 60 mV dec−1. By constructing van der Waals contact to improve the charge injection and control the carrier type, unipolar p‐type WSe2 FET with reduced hole Schottky barrier height is achieved. The complementary inverter with MoS2 and WSe2 NCFETs shows the power consumption of 68 pW.

Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures

According to quantum transport simulations, source-to-drain tunneling (SDT) has been recognized as the main cause leading to subthreshold swing (SS) saturation and degradation of short-channel MOSFETs at cryogenic temperatures. Generally, at a given low temperature, the steeper constant SS of thermionic currents may be overwhelmed by less-steep SDT currents at lower gate bias, degrading the average SS. Our simulations show that the SS of SDT currents is insensitive to temperatures for a MOSFET with a given channel length, accounting for SS saturation as lowering temperature. This work reveals the key points differentiating the possible reasons (interface traps, band tail and SDT) of SS saturation at cryogenic temperatures. We also study the impacts of carrier effective masses, gate-SD underlapping and a tunneling barrier at the source junction on SS saturation. SDT may pose a potential challenge and limit for scaling cryogenic CMOS of a quantum processor.

Spin transport in Si-based spin metal-oxide-semiconductor field-effect transistors: Spin drift effect in the inversion channel and spin relaxation in the n+−Si source/drain regions

We have experimentally and theoretically investigated the electron spin transport and spin distribution at room temperature in a Si two-dimensional (2D) inversion channel of back-gate-type spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The magnetoresistance ratio of the spin MOSFET with a channel length of 0.4$\mu$m was increased by a factor of 6 from that in our previous paper [Phys. Rev. B 99, 165301 (2019)] by lowering the parasitic resistances at the source/drain junctions with highly-phosphorus-doped n+-Si regions and by increasing the lateral electric field in the channel along the electron transport, called "spin drift". Clear Hanle signals with some oscillation peaks were observed for the spin MOSFET with a channel length of 10 $\mu$ m under the lateral electric field, indicating that the effective spin diffusion length is dramatically enhanced by the spin drift. By taking into account the n+-Si regions and the spin drift in the channel, one-dimensional analytic functions were derived for analyzing the effect of the spin drift on the spin transport through the channel and these functions were found to explain almost all the experimental results. From the calculated spin current and spin distribution, it was revealed that almost all the spins are unflipped during the spin-drift-assisted transport through the 0.4-$\mu$m-long inversion channel, but the most part of the injected spins from the source electrode are relaxed in the n+-Si regions of both the source and drain junctions. This means that the spin drift is useful and precise design of the device structure is essential to obtain a higher magnetoresistance ratio. Furthermore, we showed that the effective spin resistances that are introduced in this study are very helpful to understand how to improve the magnetoresistance ratio of spin MOSFETs for practical use.