High performance nanoscale SOI MOSFET with enhanced gate control

Abstract

A nanoscale SOI MOSFET structure with enhanced gate control is provided in this article. The gate is positioned in the silicon region's center and surrounded by insulating HfO2 and SiO2. Using this structure, we attempt to enhance the gate control over the channel. Furthermore, the source connection is positioned horizontally within the silicon region to generate an electric field caused by the potential difference between the gate and the source junction in the channel region. In fact, in addition to enhanced control of the gate over the channel, the idea of utilizing gate and source connections within the silicon region has led to the maximum electron temperature shifting from the channel to the drain region. Also, generating an undoped silicon region has been feasible to lower the lattice temperature. In addition, the electrical characteristics of the proposed MOSFET in both DC and AC states will be improved. The electrical features such as effective mobility, hot electron effect, electric field, and self-heating effect have been improved. The proposed structure is designed for RF applications and is studied in the 1 MHz to 500 GHz range. The frequency characteristics of the proposed structure, like the gate-source and gate-drain capacitors, S parameters, maximum unilateral power gain, transducer power gain, minimum noise figure, and noise conductance have also been enhanced.