Abstract
A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.
Highlights
Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells are severely limited in integration density because it is difficult to miniaturize their capacitors, so capacitorless 1T-DRAM has attracted attention as a promising alternative [1–14]. 1T-DRAM devices composed of one silicon-on-insulator (SOI) transistor have different operating mechanisms depending on their body material [15]
A 1T-DRAM device with a silicon body differentiates its state using current differences in the number of holes stored in its floating body (FB)
A silicon body 1T-DRAM device can have a small cell size of 4F2, it cannot operate as a memory in a fully depleted-SOI (FD-SOI) structure that lacks a FB hole storage region
Summary
Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells are severely limited in integration density because it is difficult to miniaturize their capacitors, so capacitorless 1T-DRAM has attracted attention as a promising alternative [1–14]. 1T-DRAM devices composed of one silicon-on-insulator (SOI) transistor have different operating mechanisms depending on their body material [15]. We show that the on current increases as the lateral GB location moves away from the electron channel due to the amount of trapped electron charge. We show that inversion current is concentrated in the 40 Å thick channel, significantly degrading the on current of this device with its lateral GB located inside the channel.
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
