Effects of Polycrystalline Silicon Plug Defect on DRAM Characteristics

Abstract

This study first demonstrates the effect of polycrystalline silicon plug defects, including voids and seams in dynamic random access memory (DRAM) storage node contact (SNC), on product characteristics. The defect portion of SNC has increased continually due to a reduction in the contact area, an increase in the doping concentration, and low-pressure chemical vapor deposition (LPCVD) process limitations. We validate the effect through defect removal experiments. Numerous methods, such as the cyclic deposition/etch/deposition process of silicon, ion implantation, and laser annealing, are used. The experiments are successful without any side effects using a high-density laser annealing process. The contact resistance of the sample-removed polysilicon defect decreases by 59% and the cell drain current increases by 6%. In addition, the overlap capacitance of the drain node and cell gate edge (Cov) variations by the SNC dopant diffusion forming the source and drain junction of the cell transistor is improved by 6%. Finally, we conduct the row precharge delay from the last data-in (tRDL) time delay reliability test using mass production test technology and it was confirmed that the contact area standard that satisfies the product quality target is improved by 10%. We propose a new direction for polycrystalline silicon SNC development for a sub-20-nm DRAM device based on this experiment.