Reflow Soldering Research Articles

Improving the mechanical performance of Sn57.6Bi0.4Ag solder joints on Au/Ni/Cu pads during aging and electromigration through the addition of tungsten (W) nanoparticle reinforcement

Sn57.6Bi0.4Ag solder has been reinforced successfully through the addition of tungsten (W) nanoparticles at a concentration of 0.5wt%. With the addition of W nanoparticles, the solder matrix lamellar interphase spacing was reduced by 31.0%. Due to the dispersion of W nanoparticles and the consequently refined microstructure, the mechanical properties of the solder alloy were enhanced, as indicated by a 6.2% improvement in the microhardness. During the reflow of solder on Au/Ni/Cu pads, the entire Au layer dissolved into the molten solder rapidly and a large number of (Au,Ni)(Sn,Bi)4 particles were formed. The fracture path of the as-reflowed joint was within the solder region, showing ductile characteristic, and the shear strength was reinforced by 8.2%, due to the enhanced mechanical properties of the solder. During the subsequent aging process, the Au migrated back towards the interface and a thick layer of interfacial (Au,Ni)(Sn,Bi)4 IMC was formed, leading to the shift of the fracture path to the interfacial IMC region, the transformation to brittle fracture and the deterioration of the strength of the joint, due to Au embrittlement. By adding W nanoparticles, the migration of Au was mitigated and the thickness of the (Au,Ni)(Sn,Bi)4 layer was reduced significantly, which reduced the Au embrittlement-induced deterioration of the strength of the joint. During electromigration, the segregation of the Bi-rich and Sn-rich phases and the accumulation of the (Au,Ni)(Sn,Bi)4 layer at cathode interface were mitigated by the addition of W nanoparticles, which improved the electromigration resistance.

Nanoindentation of Sn3.0Ag0.5Cu/ENIG Solder Joint after High Temperature Storage

This study used nanoindentation technique in order to examine the micromechanical properties of Sn3.0Ag0.5Cu (SAC305) on Electroless Nickel Immersion Gold (ENIG) surface finished Cu substrate subjected to high temperature storage. Lead free solder paste of SAC305 were soldered on ENIG substrate by reflow soldering at 215 °C for 8 second. The soldered samples were exposed to high temperature storage at 180 °C for 0, 200, 400, 600, 800 and 1000 hours. Micromechanical properties show that the solder hardness is decreasing with the HTS time from 239.13 MPa for 0 hour to 178.96 MPa for 1000 hours while the reduce modulus results has increased from 62. 16 x 103 MPa for 0 hour to 82.13 x 103 MPa for 1000 hours. The value of hardness and reduced modulus from nanoindentation approach indicate the occurrence of plastic and elastic deformation throughout the test.

RF Sensor Modules – Needs for Multifunctional Architectures

Abstract Next generation of RF sensor modules, mainly for airborne applications, will cover a variety of multifunction in terms of different operating modes, e.g. Radar, EW and Communications / Datalinks. The operating frequencies will cover a bandwidth of > 10 GHz and for realisation of modern Active Electronically Steered Antennas (AESA) the Transmit/Receive (T/R) modules have to match with challenging geometry demands, and RF requirements, like switching and filtering between different operational frequencies in transmit and receive mode. New GaN technology based MMICs, e.g. LNA, HPA are in development and multifunctional components (MFC MMICs) cover more than one RF function in one chip. Different front end demonstrators will be presented, based on multilayer ceramic (LTCC) and RF-PCB and associated assembly technologies, like chip&wire and SMD reflow soldering. These TRM front ends include a Low Noise Amplifier with an integrated Switch (LNA/SW) and for characterisation the measured Noise Figure (NF), a key characteristic for receive performance, will be compared. The need for high integration on module level is obvious and therefore specific demands for low loss ceramic and PCB based modules, packages and housings exist.

Thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components: a review

PurposeThe purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed.Design/methodology/approachLead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process.FindingsWith the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed.Practical implicationsThis literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process.Originality/valueThe unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

Time-based reflow soldering optimization by using adaptive Kriging-HDMR method

Purpose Reflow soldering process is an important step of the surface mount technology. The purpose of this paper is to minimize the maximum warpage of shielding frame by controlling reflow soldering control parameters. Design/methodology/approach Compared with other reflow-related design methods, both time and temperate of each extracted time region are considered. Therefore, the number of design variable is increased. To solve the high-dimensional problem, a surrogate-assisted optimization (SAO) called adaptive Kriging high-dimensional representation model (HDMR) is used. Findings Therefore, the number of design variable is increased. To solve the high-dimensional problem, a surrogate-assisted optimization (SAO) called HDMR is used. The warpage of shield frame is significantly reduced. Moreover, the correlations of design variables are also disclosed. Originality/value Compared with the original Kriging HDMR, the expected improvement (EI) criterion is used and a new projection strategy is suggested to improve the efficiency of optimization method. The application suggests that the adaptive Kriging HDMR has potential capability to solve such complicated engineering problems.

Integrated All Solid Micro-Supercapacitors Based on Bottom-up Silicon Nanostructures: From Nanomaterials to Cutting-Edge on-Chip Devices

Over the last two decades, Electrochemical Double Layer Capacitors (or EDLCs) attracted considerable attention since they bridge the gap between batteries and conventional capacitors by combining high energy and power density with an unmatched stability1. Moreover, the relative ease of miniaturization of EDLCs opens a wide horizon of applications such as autonomous sensor networks, active RFID…2 Although carbon is the most studied electrode material for micro-EDLCs, silicon remains the material of choice for “on-chip” integration, provided its surface area is sufficient to allow high capacitance values. Among the various strategies to design high surface area silicon nanostructures, the bottom-up CVD approach permits a fine tuning of the electrical and morphological parameters of the nanostructuresin order to obtain the highest values of capacitance, energy and power densities, while retaining high electrode conductivity and electrochemical robustness. EDLCs based on highly doped CVD silicon nanowires (Si-NWs)3 and nanotrees (Si-NTrs)4 were recently designed and proved extremely beneficial in terms of electrochemical window (4 V)5, maximal power densities (225 mW.cm-2) and cyclability (>106 charge/discharge cycles). Adding branches to Si-NWs to yield Si-NTrs also largely improved capacitance values, proving the versatility and potentiality of the bottom-up approach. However, previously published work rarely studied the influence of the morphological parameters on the supercapacitive behavior of the SiNTr-based electrodes and several steps are still required to permit “on chip” integration. In the present work, we improved previously published performances by designing advanced Si-NTrs morphologies using a simple, selective and cost effective electroless gold deposition method for the CVD catalyst deposition steps. The highly conductive Si-NTrs forests were optimized concerning “trunks” and “branches” density, length and diameters, yielding a single electrode specific capacitance value as high as 1.7 mF.cm-2with excellent cyclability and large cell voltage (using a EMI-TFSI as the electrolyte). These optimized Si-NTrs were successfully grown on microstructured interdigitated electrodes, paving the way to future integrated all-silicon “on chip” micro-EDLC. Moreover, solid state micro-EDLC were obtained combining silicon nanotrees and ionogel electrolyte, thus leading to highly stable, solder reflow resistant devices able to withstand exceptional temperature conditions with a quasi-ideal capacitive behavior. Finally, the electrode/electrolyte interface was drastically improved by highly conformal surface coatings, leading to extremely large electrochemical windows over 4 V, improved Coulombic efficiency and unprecedented cycling ability over tens of millions of charge/discharge without significant damages. (1) Simon, P.; Gogotsi, Y. Nat. Mater. 2008, (11), 845-54 (2) Beidaghi, M.; Gogotsi, Y. Energy & Environ. Sci. 2014, 7 (3), 867-884 (3) Thissandier, F. et al., Nano Energy 2014, 5, 20-27 (4) Thissandier, F. et al., J. of Power Sources 2014, 269, 740-746 (5) Berton, N. et al., Electrochem. Commun. 2014, 41, 31-34

Temperature prediction for system in package assembly during the reflow soldering process

A system in package (SiP) is a number of integrated circuits integrated into a single module. SiP can perform various functions and are often used in small systems such as mobile phones and wearable devices. The fabrication of SiP can be challenging due to their small size and high complexity. For example, during the reflow soldering process, non-uniform temperature distribution can occur, affecting the reliability of the SiP. In this study, numerical simulation is used to investigate the thermal behavior of a SiP during the reflow process and the model is validated via experimental measurements. A forced convection reflow oven was modeled using computational fluid dynamics software where the heating of the SiP assembly was performed using a conjugate heat transfer model. A complex flow field in the reflow oven was observed from the simulation results, showing a free jet region, a stagnation flow region, a wall jet region, a recirculation region, and vortices. The simulation results agreed well with experimental data. The method developed here can accurately predict the temperature distribution in a reflow oven and allow the design of temperature profiles for the reflow process that result in minimal temperature variations across the SiP assembly.

Effects of post-reflow cooling rate and thermal aging on growth behavior of interfacial intermetallic compound between SAC305 solder and Cu substrate

The interfacial reactions between Cu and Sn3Ag0.5Cu (SAC305) solder reflowed under various cooling rates were investigated. It is found that the cooling rate is an important parameter in solder reflow process because it influences not only microstructure of solder alloy but also the morphology and growth of intermetallic compounds (IMCs) formed between solder and Cu substrate. The experimental results indicate that only scallop-like Cu6Sn5 IMC layer is observed between solder and Cu substrate in case of water cooling and air cooling, while bilayer composed of scallop-like Cu6Sn5 and thin layer-like Cu3Sn is detected under furnace cooling due to sufficient reaction time to form Cu3Sn between Cu6Sn5 IMC and Cu substrate which resulted from slow cooling rate. Samples with different reflow cooling rates were further thermal-aged at 423 K. And it is found that the thickness of IMC increases linearly with square root of aging time. The growth constants of interfacial IMC layer during aging were obtained and compared for different cooling rates, indicating that the IMC layer thickness increased faster in samples under low cooling rate than in the high cooling rate under the same aging condition. The long prismatic grains were formed on the existing interfacial Cu6Sn5 grains to extrude deeply into solder matrix with lower cooling rate and long-term aging, and the Cu6Sn5 grains coarsened linearly with cubic root of aging time.

Influence of Difference Solders Volume on Intermetallic Growth of Sn-4.0Ag-0.5Cu/ENEPIG

In recent years, portable electronic packaging products such as smart phones, tablets, notebooks and other gadgets have been developed with reduced size of component packaging, light weight, high speed and with enhanced performance. Thus, flip chip technology with smaller solder sphere sizes that would produce fine solder joint interconnections have become essential in order to fulfill these miniaturization requirements. This study investigates the interfacial reactions and intermetallics formation during reflow soldering and isothermal aging between Sn-4.0Ag-0.5Cu (SAC405) and electroless nickel/immersion palladium/immersion gold (EN(P)EPIG). Solder diameters of 300 μm and 700 μm were used to compare the effect of solder volume on the solder joint microstructure. The solid state isothermal aging was performed at 125°C starting from 250 hours until 2000 hours. The results revealed that only (Cu,Ni)6Sn5 IMC was found at the interface during reflow soldering while both (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 IMC have been observed after aging process. Smaller solder sizes produced thinner IMC than larger solder joints investigated after reflow soldering, whereas the larger solders produced thinner IMC than the smaller solders after isothermal aging. Aging duration of solder joints has been found to be increase the IMC’s thickness and changed the IMC morphologies to spherical-shaped, compacted and larger grain size.

Wettability study of lead free solder paste and its effect towards multiple reflow

Nowadays, wafer bumping using solder paste has come into focus as it provides a low cost method. However, since the industries are moving towards lead-free electronic packaging, a new type of no-clean flux was produced specifically for lead-free solder paste. Therefore, this study is used to evaluate the wettability of two different types of no-clean flux onto copper substrate. Besides, its effect towards multiple reflow was also studied. Reflow soldering was conducted for both types of solder paste that contained different type of no-clean flux for up to double reflow. Two different reflow profile was used. The results showed that the Flux A exhibit better soldering performance after first and second reflow soldering. In addition, type of intermetallic compound (IMC) found after first reflow remain the same even after second reflow which was Cu-Sn based. This is shows that Flux A manage to control the diffusion process which will finally leads to a better solder joint performance. Nevertheless, mechanical testing should be carried out in order to evaluate the solder joint strength.

Effect of Flux onto Intermetallic Compound Formation and Growth

In this study, the effect of different composition of no-clean flux onto intermetallic compound (IMC) formation and growth was investigated. The solder joint between Sn 3Ag-0.5Cu solder alloy and printed circuit board (PCB) was made through reflow soldering. They were further aged at 125°C and 150°C for up to 1000 hours. Results showed that fluxes significantly affect the IMC thickness and growth. In addition, during aging, the scallop and columnar morphology of IMC changed to a more planar type for both type of flux during isothermal aging. It was observed that the growth behavior of IMC was closely related to initial soldering condition.

A Multi-agent Based Construction of the Digital Eco-factory for a Printed-circuit Assembly Line

At present, manufacturing industries are required to consider sustainability of the global environment in addition to minimization of production cost. The digital eco-factory has been proposed for a simultaneous examination of environmental performance, productivity and manufacturability. This paper entertains how to construct the digital eco-factory with high accuracy and usability. In general, the digital eco-factory is constructed on the virtual production line modelling an actual production line and its components. A multi-agent based construction of the digital eco-factory was applied and a trial digital eco-factory has been implemented for a PCA (Printed Circuit Assembly) line. A PCA line consists of a solder paste printer, two or three electronic part mounters, reflow soldering oven and testing machine. In the PCA line, processes for the above machines proceed in sequence, these machines’ capabilities are modelled as individual machine agents. There are several types of printed boards produced, depending on the number of mounted electronic components and the temperature of the solder. When a blank PCB (Printed Circuit Board) is input to a solder paste printing machine, the production process is started. A PCB is modelled as a part agent which is one of the product agents. For some example virtual productions, power consumption of each machine on each line from the environmental view and productivity of each machine and each line are monitored. From the results of the trial implementation, it can be said that all components on the production line could be configured as software agents with required accuracy. These agents are called “machine agents.” In addition to machine agents, manufactured products such as workpiece and parts are also configured as software agents.

生産システム設計・改善時における生産性と消費エネルギ量のシミュレーションシステム（設備故障を考慮する場合のエネルギ原単位のロットサイズ依存に関する研究）

Industries have been becoming more important to evaluate and reduce energy consumption when designing, operating, and improving manufacturing systems. In our past research, manufacturing system simulation to evaluate productivity and energy consumption concurrently has been proposed and developed for designing, operating, and improving the manufacturing systems. We also proposed a formulation for relationships between lot size and energy consumption per unit of production throughput. However, on our proposed formation, we did not consider the breakdown states in each facilities. In this paper, we propose a formulation concerning relationships between lot size and energy consumption per unit of production throughput considering breakdown states. This proposed formulation is an approach for the theoretical realization of the production conditions that affect a productivity or energy consumption. We investigate the formulation of the relationship between energy consumption and production throughput taking into account breakdown states, and verify it by using our developed simulation. Concerning the investigation, a middle-scale semiconductor manufacturing line which consist of three facilities, a solder printing facility, an IC mounting facility, and a solder reflow facility is simulated. Through the investigation, the relation between lot size and energy consumption per production throughput, production throughput are being understood.

Embedded Die Packages and Modules for Power Electronics Applications

Packages and modules with embedded semiconductor dies are of interest for various application fields and power classes. First packages in the lower power range are available in volume production since almost six years. Recent developments focus on medium and higher power applications raging over 500W into the kW range. Different approaches are available to realize such packages and modules. This paper will give an overview and detailed description of the latest approaches for such embedded die structures. In common of all of these approaches, is the use of laminate based die embedding, which uses standard PCB manufacturing technologies. Main differences are the used base substrate, which can still be a ceramic (DBC), Cu leadframe or high current substrate. Examples for the different methods will be given. As the main part, this paper will describe concepts, which enable significant smaller form-factor of power electronics modules, thereby allowing for lower price, high reliability, capability of direct mounting on e.g. a motor so as to form one unit with the motor housing, wide switching frequency range (for large application field) and high power efficiency. The innovative character of this packaging concept is the idea to embed the power drive components (IGBTs, MOSFETs, diode) as thinned chips into epoxy-resin layer built-up and to realize large-area interconnections on both sides by direct copper plating the dies to form a conductor structure with lowest possible electrical impedance and to achieve an optimum heat removal. In this way a thin core is formed on a large panel format which is called Embedded Power Core. The paper will specifically highlight the first results on manufacturing an embedded power discrete package as an example of an embedded power core containing a thin rectifier diode. For module realization, the power cores are interconnected to insulated metal substrates (IMS) by the use of Ag sintering interconnection technologies for the final manufacturing of Power modules. The paper will elaborate on the sintering process for Power Core/IMS interconnections, the microscopically features of the sintered interfaces, and the lateral filling of the sintering gap with epoxy prepregs. Firstly, 500W power modules were manufactured using this approach. Reliability testing results, solder reflow testing, temperature cycling test and active power cycling, will be discussed in detail.

Solder-reflow resistant solid-state micro-supercapacitors based on ionogels

All-solid-state micro-supercapacitors with silicon nanowire electrodes and ionogel thin film electrolyte showed improved frequency response and a sustained solder reflow process.

A High Performance Power Module with >10kV capability to Characterize and Test In Situ SiC Devices at >200°C Ambient

Abstract This paper presents design, fabrication and characterization details of a 10kV power module package for >200°C ambient temperature applications. Electrical simulations were performed to confirm the module design, and that the electric field distribution throughout the module did not exceed dielectric capabilities of components and materials. A suitable copper etching process was demonstrated for DBC layout, and a high melting point Sn/Pb/Ag solder reflow process was developed for device and component attachment. To monitor the operational temperature of the module, a thermistor was integrated onto the substrate. A new silicone gel, having a working temperature up to 210°C, was evaluated and selected for encapsulation and, of great importance, for passivation of high voltage (10kV) SiC dies. An additive manufacturing ‘Design Process’ was developed and applied to printing the housings, molds, and test fixtures. Also, cleaning processes were evaluated for every step in the fabrication process. To verify performance of the modules, mechanical dies were mounted on the substrates, and a high temperature testing setup built to characterize the modules at high temperature. Measurements indicated that the module can operate up to 12kV within 25°C to 225°C, with less than 0.1 μA leakage current. The packaging was used for full-power characterization of developmental 10kV SiC diodes, and proved that the power module packaging satisfied all requirements for high voltage and high temperature applications. This work successfully validated the processes for creating high voltage (>10 kV) and high temperature (>200°C) power modules.

Lattice Boltzmann method study of bga bump arrangements on void formation

This paper studies effects of different bump orientations on the void formation using Lattice Boltzmann method (LBM) based software. Prediction of air void is vital typically at the onset of reflow soldering which could reduce the reliability of the mold cavity. The effect of variations in pressure and velocity of the mold during flow on the formation of air voids are investigated for three different ball grid array (BGA) orientations namely perimeter, middle empty and full. The findings identified the predicted locations of void formation during the underfill encapsulation process. It was shown that middle empty orientation has the highest potential of void formation typically towards the end of mold flow as a result of low pressure and high velocity flow. In addition, using high bond number and high viscosity material could further reduce the air void formation.

Energy Efficiency Analysis of Vapor Phase Soldering Technology through Exergy-Based Metric

In electronics production, the condensation based soldering technologies are known for reproducible solder profiles and efficient heat transfer methodology. The recent advancements in lead-free soldering and requirements for absolute void-free interconnections to increase the reliability and lifetime of the product needs optimization of the soldering process. The vacuum assisted vapor phase soldering process addresses the requirements with respect to mass production and parallelly resource efficient production which is also the motivation for the present work. This study is devoted to quantify the resource consumption and qualify this consumption through exergy flows in a vacuum vapor phase reflow soldering technology in electronics manufacturing.The analysis implies on the saving potential for energy consumption specifically during the vacuum process which also defines the void reduction quality of solder joints. Exergy efficiency analysis of a temperature profile depicts the influence of the materials used in the demonstrator. Shortening the production lead‑time, and increasing the production rate increase the efficiency of exergy and prevents wastage of usable energy. Furthermore, the set-up improvements for the temperature profiles processes are necessary, and the changes toward developing new, transformational technologies in pre-heating and vacuum zones are mandatory if a high efficiency of resources used is aimed.

Microstructure and mechanical properties of Pb-free Sn–3.0Ag–0.5Cu solder pastes added with NiO nanoparticles after reflow soldering process

Incorporating various types of ceramic type nanoparticles into Pb-free solder pastes produces unique nanocomposite solder pastes. In this study, Sn–Ag–Cu (SAC) 305 solder alloys were mixed with 0.5, 1.5, and 2.5wt.% NiO ceramic nano-elements to produce a new set of nanocomposite solder pastes. The displacement phenomenon of NiO nanoparticles during reflow soldering process may contribute efficient idea in the field of microelectronic industries. The reinforcement of reactive nanoparticles in SAC 305 solder paste caused 50% changes in the intermetallic layer thickness and hardness of plain solder. Top-view microstructural analysis wherein dimple surfaces were magnified showed that the combination of SAC 305–2.5wt.% NiO nanopaste exceeded the limits of alloy addition.

Microstructural Evolution of Lead-Free Solder Joints in Ultrasonic-Assisted Soldering

Solder joint reliability greatly depends on the microstructure of the solder matrix and the morphology of intermetallic compounds (IMCs) in the joints. Addition of strengthening phases such as carbon nanotubes and ceramic particles to solder joints to improve their properties has been widely studied. In this work, ultrasonic vibration (USV) of casting ingots was applied to considerably improve their microstructure and properties, and the resulting influence on fluxless soldering of Cu/Sn-3.0Ag-0.5Cu/Cu joints and their microstructural evolution was investigated. It was demonstrated that USV application during reflow of Sn-based solder had favorable effects on β-Sn grain size refinement as well as the growth and distribution of various IMC phases within the joints. The β-Sn grain size was significantly refined as the ultrasound power was increased, with a reduction of almost 90% from more than 100 μm to below 10 μm. Long and large Cu6Sn5 tubes in the solder matrix of the joints were broken into tiny ones. Needle-shaped Ag3Sn was transformed into flake-shaped. These IMCs were mainly precipitated along β-Sn phase boundaries. High-temperature storage tests indicated that the growth rate of interfacial IMCs in joints formed with USV was slower than in conventional reflow joints. The mechanisms of grain refinement and IMC fragmentation are discussed and related to the ultrasonic effects.