Solder Ball Research Articles

Size-on-demand preparation of SAC305 solder balls based on pulsated orifice ejection method

Drop-on-demand ejection of solder droplets has significant potential applications in field such as ball grid array packaging and microcircuit printing. To apply this technique successfully, it is important to ensure stability during the ejection of droplets and control the size of the droplets accurately as required. In this study, the pulsated orifice ejection method (POEM) is used to investigate the relationship between key parameters and the stability and size of SAC305 droplet ejection. Additionally, the microstructural morphology changes in solder balls with different sizes are investigated. Reducing the duration of the tup, increasing of voltage, and decreasing rod distance all lead to bigger solder balls. To achieve stable and size-on-demand droplet ejection, key parameters should be coordinated to ensure the deviation between the actual solder ball size and the target solder ball size remains within a range of ±10 μm. Observation and analysis of the microstructure reveal that as the size of solder ball increase, the cooling rate decreases rapidly, resulting in significant differences in the dendritic growth within the solder balls. This study presents an effective method and parameter selection for the drop-on-demand droplet ejection process, providing a solid foundation for direct solder bump deposition and microcircuit printing.

The characterization of low-k thin films and their fracture analysis in a WLCSP device

The IC industry implements low dielectric constant (low-k) materials in copper/low-k interconnects to reduce the RC delay and crosstalk noises. As low-k dielectrics are weaker than traditional SiO2, measuring their mechanical properties is important for numerical simulations to evaluate the structural integrity of a package with low-k materials. In this study, we fabricated freestanding samples of low-k thin film with/without pre-cracks on both sides using lithography and exfoliation for uniaxial tension and coefficient of thermal expansion tests. The tension tests revealed that the average fracture toughness and Young's modulus of the low-k film are 1.41 MPa·m1/2 and ∼2.5 GPa, respectively. Using the measured mechanical properties, we performed a fracture analysis by a 2D finite element model for the low-k material in a wafer-level chip-size package under thermal loading. The computational results showed that the critical microcrack in the low-k layer occurs near the solder balls, where the KI increases rapidly with crack length and exceeds KIC. The results are consistent with the experimental findings in literature. The present methods can help evaluate the integrity of low-k material in a package and improve reliability.

MICROSTRUCTURE AND INTERFACIAL INTERMETALLIC OF Sn-3.0Ag-0.5Cu/Sn-58Bi SOLDER JOINT FOR PACKAGE-ON-PACKAGE TECHNOLOGY

In this study, the effect of growth microstructure on diffusion and intermetallic compound of Sn-58Bi/SAC305 solder joint with different of SAC305 size and reflow temperature had been studied. For effect of different size, it used 180°C reflow temperature and 5minute reflow time with the size of SAC305 solder ball was 800μm, 900μm and 1000μm. For the reflow temperature would reflow at 160°C,170°C, 180°C, and 190°C for 5minute reflow time. After the reflow process, a sample would go through a several processes such as molding, grinding and polishing before undergoing material characterization. The diffusion area had shown an inversely relationship with SAC305 size and linearly relationship with temperature and time reflow. Besides, the IMC thickness was thinner with increasing of SAC305 size. In this finding, the area of Sn-58Bi/SAC305 solder joint could be predicted to enhance the package on package technology.

Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions.

Flip Chip Ball Grid Array (FCBGA) packages, together with many other heterogeneous integration packages, are widely used in high I/O (Input/Output) density and high-performance computing applications. The thermal dissipation efficiency of such packages is often improved through the use of an external heat sink. However, the heat sink increases the solder joint inelastic strain energy density, and thus reduces the board-level thermal cycling test reliability. The present study constructs a three-dimensional (3D) numerical model to investigate the solder joint reliability of a lidless on-board FCBGA package with heat sink effects under thermal cycling testing, in accordance with JEDEC standard test condition G (a thermal range of -40 to 125 °C and a dwell/ramp time of 15/15 min). The validity of the numerical model is confirmed by comparing the predicted warpage of the FCBGA package with the experimental measurements obtained using a shadow moiré system. The effects of the heat sink and loading distance on the solder joint reliability performance are then examined. It is shown that the addition of the heat sink and a longer loading distance increase the solder ball creep strain energy density (CSED) and degrade the package reliability performance accordingly.

Mechanical properties of Sn–Pb based solder joints and fatigue life prediction of PBGA package structure

Solder joints are generally the weakest part in electronic packaging structure whose fatigue life depends to a large extent on the durability of solder joints. In pursuit of a balance between environmental protection and soldering performance, commonly used Sn–Pb solder should be modified by adding other chemical elements to reduce Pb content. This work aims to investigate the performance of different solder materials and explore the impact of different electronic package structures. Firstly, tensile experiments are performed on three kinds of solders (Sn–Pb, Sn–Pb–In, Sn–Pb–Bi) to obtain their mechanical behavior, and then the constitutive laws of them are calibrated by Anand model. Additionally, finite element method (FEM) is used simulate the response of plastic ball grid array (PBGA) package structure under thermal cycles, and mechanical variables including deformation, equivalent stress, and equivalent strain are analyzed. Finally, Coffin-Manson and Engelmaier equations are adopted to predict the fatigue life of package structures and the effects of various factors such as solder materials, dimensions of components, and welding quality are further investigated. Results reveal that adding Bi into Sn–Pb solder can make the solder joints have better performance. From the perspective of optimum fatigue life, the plastic package thickness is recommended in the range of 0.8 mm–0.9 mm, the chip thickness is recommended as 0.35 mm, the substrate thickness is recommended to be less than 0.34 mm, and the ratio of stand-off height to solder ball diameter should be controlled between 0.6 and 0.7. According to the prediction, the solder ball diameter is suggested to be 0.54 mm so that fatigue life could reach 194 cycles, and the stand-off height for this package structure is suggested to be 0.36 mm so that fatigue life could reach 123 cycles.

Refined simulation method and failure study of BGA package structure based on image drive

The packaging structure, internal defects, and external loads have a significant impact on the reliability and ultimate failure of chip performance. Therefore, establishing a refined model that considers multiple factors is of great significance for improving the reliability and optimizing design of packaging structures. For this purpose, this study firstly adopts CT scanning technology to reconstruct the ball grid array (BGA) package structure in three dimensions, optimize the finite element meshing, and analyze the drop behavior by using the finite element method based on nonlinear damage instantiation. In addition, to further investigate the effect of fine defects on the failure of the package structure, a simulation of the damage evolution behavior of a real defective solder ball structure under impact loading is implemented with the help of submodeling techniques. The research results provide a technical reference for the reliability analysis and multi-occasion structure design of aerospace BGA package structures.

Cost-Effective Broadband and Compact Patch Antenna Based on Ball Grid Array Packaging for 5G NR FR2 Band Applications

This brief introduces a compact, cost-effective broadband patch antenna based on ball grid array (BGA) packaging technology for 5G millimeter wave new radio (NR) FR2 band application. Based on the low-cost FR-4 substrate and single-layer configuration, the patch antenna achieves an ultra-low cost, which is attractive for large-scale 5G millimeter-wave array applications. Parasitic patches are added to the antenna to obtain broadband impedance bandwidth. To further reduce the antenna size and eliminate bulky connectors, solder balls are added to form a BGA package with connectorless interconnects. Consequently, the proposed antenna element achieves a compact size of 5.2 mm × 3.2 mm × 1.4 mm. Antenna elements and 1 × 8 array prototypes have been fabricated and verified. The measurement results show that the proposed antenna element has a -10 dB bandwidth of 56.1% (20-35.6 GHz), fully covering the 5G millimeter wave n257 (26.5-29.5 GHz), n258 (24.25-27.5 GHz), and n261 (27.5-28.35 GHz) bands. The maximum realized gains of the antenna elements and the 1 × 8 array prototype are 7.2 dBi and 13.9 dBi, respectively.

Effect of Heating Power on Ball Grid Array Thermal Shock Reliability for a Fanout Package

Abstract The reliability of Fanout package with a ball grid array (BGA) for microsystem is studied under thermal shock. Different heat source powers are applied to the silicon substrate to imitate the power dissipation induced heat of power devices and the thermal fatigue life of the package are studied using the Anand constitutive model and Darveaux life model. The finite element method simulation results show that the thermal fatigue life is not positively correlated with the heat source power. In a certain power range, the life first increases and then decreases. To explain this abnormal phenomenon, the fatigue analysis of solder balls with different heating power (10–55 W) is carried out. The results show that in the low temperature stage, with the increase of the heat source power, the heat source offsets the low temperature effect to a certain extent, and the stress value of the solder balls decreases. And during the high temperature stage, the stress of the ball is hardly affected. However, with the increase of the heat source power, the thermal deformation of the structure is gradually serious, the effect of offsetting the low temperature effect is reduced, and the thermal fatigue life increases with the increase of the heat source power. The results of the paper can be useful for microsystem package design.

Morphologies and nucleus models of β-Sn grains in SAC305-xIn freestanding solder balls and solder joints

Morphologies and nucleus models of β-Sn grains in SAC305-xIn freestanding solder balls and solder joints

Preparation and performance of Sn-based composite solder joints by solid-liquid low-temperature solder bonding technology

In the era of big data, the advantages of 3D packaging are becoming increasingly significant. In addition, the mismatch between the coefficient of thermal expansion (CTE) of the PCB and BGA components leads to dynamic warpage of the system, and the expansion and innovation of low-temperature soldering have been a new trend. We developed a fully mixed solder joint of a SAC305(Sn-3.0Ag-0.5Cu wt.%) solder ball and Sn–58Bi(wt.%) solder paste by solid-liquid low-temperature solder bonding technology. The mixing degree and diffusion process of the two were calculated and simulated by mathematical calculation and COMSOL Multiphysics. The results show that a completely mixed solder joint can be obtained after reflow at 210 °C for 5 min. The average shear strength of the composite solder joints was 63.68 ± 1.12 MPa, which was about twice that of the single SAC305 and Sn58Bi solder joints, and the shear fracture was a composite mode of brittle and ductile fracture, which appeared in the IMC and the solder, respectively. After complete mixing, the solder wettability angle was less than 26.68°, with outstanding wetting properties. No phase transition occurred after aging, the distribution of each phase remained uniform, and no enrichment of the brittle phase was observed at the interface. The shear strength decreased slightly with aging time, and the reduction value was less than 10 MPa, which has good reliability.

Automated coplanarity inspection of BGA solder balls by structured light

The coplanarity of BGA (Ball Grid Array) solder balls is critical for reliable connectivity in semi-conductor units. However, existing ball height inspection techniques require high-cost equipment and skilled operators, which are not feasible for using in real-time manufacturing process. In this paper, a fast measurement method of coplanarity inspection of solder balls is developed based on structured light technique. The hardware of the system includes a camera and a projector. The digital-light-processing (DLP) projector emits programmed image patterns and the digital complementary-metal-oxide-semiconductor (CMOS) camera captures distorted image patterns on solder balls. The image processing software is developed to compare the original and distorted image patterns to reconstruct the three-dimensional (3D) solder balls. The method has been calibrated extensively and exhibits accuracy within 5 μm mean squared error compared to ground truth values determined by X-ray computed tomography. The proposed method achieves reliable, in-line ball height measurement and could be potentially used for real-time in-line coplanarity inspection of BGA chip during manufacturing.

Deformation behaviors of flip chip plastic ball grid array packages subjected to temperature change using moiré interferometry

When the temperature of the package assembly is changed, non-uniform deformation and local stress may occur owing to the different thermal expansion coefficients of the constituent materials, while concentrated thermal stress may cause significant failure. In this study, we carry out an experiment and analysis of the thermal deformation of a flip chip plastic ball grid array package with respect to temperature change. Interference fringe patterns representing the displacement distribution of each temperature stage are obtained using a Moiré interferometry and the bending deformation behavior and the strain of the solder ball are analyzed thereafter. We compare the deformation behavior of a single-sided package assembly and a double-sided package assembly. The effective strain, which significantly affects the failure of the solder ball, is found to be the largest in the solder ball just outside the edge of the chip in the case of the single-sided package assembly. In the case of the double-sided package assembly, the maximum effective strain is found in the solder ball just inside the edge of the chip, with a value approximately 50 % larger than in the case of the single-sided package assembly. Wenn sich die Temperatur eines Gehäuses ändert, kann es aufgrund der unterschiedlichen Wärmeausdehnungskoeffizienten der einzelnen Werkstoffe zu ungleichmäßigen Verformungen und lokalen Spannungen kommen, während konzentrierte thermische Spannungen zu erheblichen Ausfällen führen können. In dieser Studie führen wir ein Experiment und eine Analyse der thermischen Verformung einer Flip-Chip Kunststoffkugel Gitteranordnung in Abhängigkeit von der Temperaturänderung durch. Mit Hilfe der Moiré-Interferometrie werden Interferenzstreifenmuster aufgenommen, die die Verschiebungsverteilung jeder Temperaturstufe darstellen und anschließend werden das Biegeverformungsverhalten und die Dehnung der Lötkugel analysiert. Wir vergleichen das Verformungsverhalten einer einseitigen und einer doppelseitigen Gehäusebaugruppe. Es zeigt sich, dass die effektive Dehnung, die das Versagen der Lötkugel maßgeblich beeinflusst, im Fall der einseitigen Baugruppe in der Lötkugel direkt außerhalb des Chiprands am größten ist. Bei der doppelseitigen Baugruppe ist die maximale effektive Dehnung in der Lötkugel direkt innerhalb des Chiprands zu finden, mit einem Wert der etwa 50 % größer ist als bei der einseitigen Baugruppe.

Hypo-eutectic microstructure formation and nanomechanical response in Sn-3.0Ag-0.5Cu solder balls: Effects of undercooling

The microstructure control and refinement in length scale are pursued in the development of next generations of Pb-free solder alloys with high reliability in harsh environments. In the present work, the influences of nucleation undercooling, as brought by solder ball size, over the microstructure evolution and nanomechanical behavior in Sn-3.0Ag-0.5Cu (wt%) Pb-free solder alloys, have been quantitively investigated using Differential Scanning Calorimeter (DSC), Scanning Electron Microscopy (SEM) and nanoindentation. The results reveal that undercooling increases with the decrease of solder ball size. The frequency of interlaced grain microstructure was significantly increased in 200 μm balls, with a further increase of undercooling by ~10 K. The volume fraction of primary β-Sn increased with larger undercooling, leading to microstructure refinement with a finer spacing of both β-Sn dendrite and eutectic Ag3Sn. The length scale of refinement is on the order of ~2, as the solder ball size reduced from 650 μm to 200 μm. Nano-hardness and creep resistance increase with smaller ball size and larger undercooling. Nano-hardness values are relatively higher as more eutectic regions being measured due to the strengthening effect of finer and denser eutectic Ag3Sn, and also the refinement of interlaced β-Sn grains. The creep exponent is insensitive to the loading force or solder ball size. The variation of nanomechanical deformation behavior was reduced in the 200 μm balls, due to the substantial microstructure refinement, while the dominant creep mechanism stays as the dislocation climb for various solder ball sizes.

Intelligent defect inspection of flip chip based on vibration signals and improved gcForest

The defect inspection of flip chips has become a meaningful and challenging task with the decrease of size and distance of solder balls. In this paper, we proposed a novel defect diagnostic method for flip chips based on vibration signals and improved multi-grained cascade forest (gcForest). Firstly, the flip chip is excited by an air-coupled capacitive ultrasonic transducer, and the corresponding vibration signals of flip chip are captured by a laser scanning vibrometer. Then, the feature information of original vibration signals is extracted by muti-grained scanning (MGS) automatically. Finally, the extracted feature information is input into the cascaded forest for defect diagnosis. Considering the low data transmission efficiency and feature redundancy between MGS and cascaded forest, a feature extraction channel strategy based on kernel principal component analysis (KPCA) is introduced into the cascaded forest. Besides, in order to improve the generalization ability of the improved gcForest, the classifiers of each layer in cascade forest are upgraded. The results demonstrate the superiority of the improved gcForest over the traditional methods on experimental vibration data of flip chips, especially under small training sizes, which is very beneficial to practical engineering.

Impact of Isothermal Aging on Mechanical Properties of 92.8%Sn-3%Ag-0.5%Cu-3.3%Bi (Cyclomax) Solder Joints

During operation, electronic components are exposed to high temperatures that may last for long periods, depending on the operating duration. Solder joints are one of the components most affected by thermal aging while in service. In this research, the effect of thermal aging duration and temperature on the mechanical properties of 92.8%Sn-3%Ag-0.5%Cu-3.3%Bi (Cyclomax) was investigated. The novelty of this work lies in the study of the important properties of a new generation of Sn-Ag-Cu (SAC) materials (i.e., Cyclomax). Cyclomax is rare in industry and immature in research. To understand the effect of thermal aging, the microstructure was investigated, and changes in it and its mechanical properties were observed. To simulate solder joints in electronic devices, samples of solder balls were prepared and attached to copper pads on electronic boards. Most samples were then treated at 150 °C or 100 °C for up to 1000 h and some samples were left untreated for comparison. A scanning electron microscope (SEM) was used to obtain images of the microstructure. The shear stress–shear strain relationships, including the ultimate shear strength (USS), the modulus of elasticity and the ultimate energy (UE), were investigated. The microstructure images indicated the presence of a layer of Cu6Sn5 on top of the copper pad before thermal aging was applied. The thickness of this layer increased with the application of thermal aging over time. The results for the shear stress–shear strain relationship indicate that all of the USS, the total energy (TE) to shear off the solder balls and the UE decreased at the beginning of the thermal aging and then reversed to increase later. In general, isothermal aging reduces the performance of Cyclomax solder joints in terms of the minimum force and energy required to separate and subsequently damage electronic components.

Study on the Influence of Vacuum Vapor Phase Soldering Process Technology on SiP Component

Vapor phase soldering (VPS) is used in the assembly of highly reliable electronic products for aerospace, military, and industrial area for the advantages of heat transfer coefficient, good temperature uniformity, and controllable maximum soldering temperature. VPS is usually used for PCB (Printed Circuit Board) and complex components. However, little research has been done on the application of VPS process technology on the SiP (System in Package) component in the process of solder ball or solder column package. In this work, we investigated the influence of the vacuum VPS process on the SiP component. The advantages of VPS and vacuum process were discussed and the maximum shear strength of solder joints in the vacuum process was calculated. The vacuum process has no impact on the internal structure of the SiP component.

Effects of Voids on Thermal Fatigue Reliability of Solder Joints on Inner Rings in Ball Grid Array Packaging by Finite Element Analysis

Under alternating temperatures, the fatigue failure of solder balls caused by the mismatch of the thermal expansion coefficient is a key problem in a Ball Grid Array (BGA). However, the combined effects of the solder ball location and the size of voids within it can seriously affect the thermal fatigue reliability of BGA solder balls, which can be easily ignored by researchers. Firstly, the thermal fatigue reliability of the board-level solder balls was evaluated by a temperature cycling test of the BGA package at -20 °C-+125 °C. The experimental results showed that the thermal fatigue reliability of the outer ring's solder joint was lower than that of the inner ring. Secondly, the reliability of the solder balls in the BGA package was studied under the same thermal cycling condition based on finite element analysis (FEA). The influences of voids on fatigue life were investigated. Generally, a linear correlation between the void content and the fatigue life of the inner rings' solder balls could be identified with a gradually smoothed relationship for solder balls closer to the center. In addition, when the size of the void exceeded a critical volume, the inner ring's solder ball with the void would fail before the outermost ring. The results of FEA showed that the critical void volume ratio from the second to fifth ring increased from 10.5% to 42.3%. This study provides a valuable reference for the influence of voids on the thermal fatigue reliability of BGA solder balls.

The Impact of the Connection Failure of Ground Solder Balls on Digital Signal Waveform

Ball-grid array (BGA) packages are widely used in digital signal devices, whose reliability and signal integrity are critical. In this research, the impact of failed ground solder balls on digital signal waveforms was theoretically modeled and analyzed, and the results were experimentally verified. A 3-D electromagnetic field model of a digital signal transmission channel with failed ground solder balls was developed to analyze the signal transmission in the frequency domain. In addition, a time-domain waveform simulation system was developed to examine the changes in the digital signal waveforms before and after degradation. Based on the structural and signal transmission characteristics of the solder area with failed ground solder balls, an equivalent circuit model of the degraded solder area was developed, which accurately predicts the effect of the failed ground solder balls on the amplitude and rising edge of the digital signals. The results obtained from the simulation were validated using experimental tests. This study fully examines the effects of the location and number of failed ground solder ball on signal transmission in both the frequency and the time domain. It provides insight and guidance regarding the impact on signal integrity of such faults, which serves to assist in improved packaging reliability and the development of fault detection strategies for such electronic systems.

Microstructure and morphology of the soldering interface of Sn–2.0Ag–1.5Zn low Ag content lead-free solder ball and different substrates

Eutectic Sn–Ag–Cu lead-free solder has limited applications due to cost and reliability issues. Sn–Ag–Zn solder has the advantages of low melting point, good mechanical properties and reliable welding interface. However, the research system of low silver content Sn–Ag–Zn solder is incomplete. In this paper, Sn–2.0Ag–1.5Zn low silver content alloy solder is soldered to different substrates. The interfacial reaction after soldering and the microstructure and reliability under different aging treatment conditions are studied. Sn–2.0Ag–1.5Zn solder is made into solder balls by direct melting method. The solder balls are placed in a solder strength tester to be heated and welded to the substrate, and then the solder joints are placed in a heating furnace for aging treatment. The results show that the solder is soldered to the bare Cu substrate, and a dense double-layer Intermetallic Compound (IMC) structure of Cu5Zn8 and Ag3Sn is formed at the interface after aging treatment. The double-layer structure blocks each other, limiting the development of copper-tin IMCs. The solder is soldered with the Cu substrate electroplated with Ni barrier layer, and the soldering interface forms a thin layer of Ni3Sn4 metal compound. After aging for 1000 h, the thickness of Ni3Sn4 is about 1 μm, the thickness of Ni barrier layer is kept at 2–3 μm, and the barrier effect of Ni barrier layer is stable. Sn–2.0Ag–1.5Zn solder has excellent loss performance in long aging treatment. It has good heat-resistance aging treatment, good quality of solder connection, high interface reliability and less environmental pollution. The low silver content in Sn–2.0Ag–1.5Zn solder results in a significant cost reduction. Coarse IMC Ag3Sn is not easily formed. The optimized ratio of Ag and Zn in Sn–2.0Ag–1.5Zn solder improves the strength and toughness of the solder joint. The performance has been improved, and it is a very promising alloy solder.

DDR4 Ball Grid Array Package Intermittent Fracture Effect on Signal Integrity

DDR4 die are commonly packaged in Ball Grid Array packages. The package solder balls develop fractures due to difference in the thermal co-efficient of expansion of the package and printed circuit board. The intermittent behavior of the fracture is due to the momentarily opening of the solder joint due to vibration or the warpage of the package and the printed circuit board. This intermittent behavior can result in no fault found phenomenon in memory systems. DDR4 response in the presence of an intermittent fracture depends on the location of defect. The defect can occur in clock, address or data channel. A test fixture is used to show the AC coupling nature of fracture in ball grid array package solder ball. The intermittent change in the height of fracture is analyzed using 3-D electromagnetic model of the solder ball using high frequency structure simulator (HFSS) software. HFSS model of the fractured solder ball is used along with DDR4 channel topology to compare the sensitivity of clock, address and data channel response to intermittent fracture. It is shown that the data channel is most sensitive to intermittent fracture. DDR4 data mask violation occurs for even a small fracture height of 0.1 μm. For clock channel, the eye degrades or becomes smaller as the fracture height increases from 0.1 μm to 3 μm. But even for 3 μm fracture height, clock eye diagram remains within DDR4 clock +/- 110 mV specification. For address channel the eye degrades or becomes smaller when the height of fracture increases from 0.1 μm to 3 μm. For fracture height of 3 μm, DDR4 address +/- 65 mV input specification violation occurs. Address channel is more sensitive to intermittent fracture as compared to clock channel. The analysis shows that there is always intermittent error in data channel due to intermittent fracture and there are more intermittent errors in address channel compared to clock channel.