Soft Error Rate Reduction Research Articles

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100%<; area overhead <; 200%, the solutions of MIX have lower SER (SER reduction >81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).

CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics

The effects of soft error in combinational logics are challenged by decreasing the feature size of transistors in nanoscale technologies. Moreover, the single event transients (SETs) caused by particle strikes, manifesting multiple event transients (METs), are expectable, as well. Coping with this problem is the end of CLEAR using a cross-layer method as an effective way to mitigate the rate of double event transients (DETs) in combinational logic. First, an algorithm is proposed based on local displacements and linear programming (LP) optimization problem, which locates the cells in the best way from the DETs point of view. Next, two hardening methods are proposed based on resizing and fault masking. Finally, one of these two methods is applied to the aforesaid algorithm results, modified layout, considering the given design parameters. Experimental studies reveal a reduction of 42.9% on average in DETs rate, which can be improved up to 51.1% and 68.9% by applying two aforementioned hardening methods with some negligible overhead.

Impact of Single-Event Upsets on Convolutional Neural Networks in Xilinx Zynq FPGAs

Convolutional neural networks (CNNs) are quickly becoming an attractive solution for autonomous vehicles, military weapons, and space exploration. Thanks to their reconfiguration ability, design flexibility, and low power consumption, field-programmable gate arrays (FPGAs) have become a promising candidate for CNN accelerators. However, FPGAs have been proven to be susceptible to radiation-induced single-event upsets (SEUs). One goal of this article is to analyze the impact of quantization on the reliability of CNNs in FPGAs. Therefore, we performed quantization on ZynqNet without affecting its classification accuracy. Meanwhile, we implemented the triple modular redundancy (TMR) version of ZynqNet and we also evaluated the effects of SEUs on these CNNs through both fault injections and neutron exposures. Fault injection results show that TMRed ZynqNet reduces the soft error rate (SER) by 33.59% with a circuit area increase of 111.92% when compared with the standard ZynqNet. The experimental results demonstrate that the quantized ZynqNet reduces the SER by 71.36% with a circuit area reduction of 44.76% when compared with the standard ZynqNet. These results confirm that quantization does contribute to SER reduction of the neural networks. In addition, the operating system on the processing system (PS) side was also found to be highly sensitive to SEUs, and, thus, mitigation techniques should be applied.

Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring Approach

Traditionally, increasing logical masking probability has been used to improve the circuit reliability against single-event transients (SETs). As the very first work, this paper presents a new approach to increase the reliability of digital circuits against soft errors caused by multiple event transients (METs) by taking advantages of circuit partitioning and local logical restructuring techniques. In the proposed approach, the circuit is partitioned into various subcircuits and, then, several structures of each subcircuits which satisfy the area constraints are extracted by using a graph-based procedure. In order to select the suitable alternative between various subcircuit structures, we introduce a novel metric named global failure probability in the presence of METs (GFPM). This parameter provides an evaluation of each subcircuits contribution in the soft error rate (SER) of the given circuit making it possible to estimate the impacts of changing the structure of the subcircuits on the circuit SER. Hence, it prevents from repeatedly calculating the SER of the circuit that is very time-consuming leading to significant improvements in the optimization runtime. Experimental studies on ISCAS benchmark circuits show that the proposed approach, on average, achieves 18.4% SER reduction with 11.9% area overhead and 8.2% delay overhead comparing to the original circuit while the global SET-based SER mitigation approach and the global MET-based SER mitigation approach achieve 8.46% and 21.8% SER reduction, respectively. Besides, the proposed technique is about $580 \times $ faster than the global MET-based method.

Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme

Due to the reduction in device feature size and supply voltage, achieving soft error reliability in sub-micrometer digital circuits is becoming extremely challenging. We consider the problem of choosing the gate sizes in a combinational logic circuit in order to minimize the soft error rate (SER) of the circuit. This problem can be solved using the heuristic as well as the greedy-based approaches for small-size problems; however, when the circuit size increases, the computational time grows exponentially, and hence, the previous methods become impractical. This paper proposes a novel technique for soft error tolerant design of large-scale combinational circuits using a cone-oriented gate sizing. Circuit partitioning is used to split the circuit into a set of small sub-circuits. The gates of sub-circuits are resized, such that the entire circuit SER is reduced based on a new soft error descriptor metric. The proposed cone-oriented gate sizing framework is used for selective gate sizing, leading up to 31% SER reduction with less than 17% area overhead when applied to large-scale benchmarks. The results also show that the proposed method is 21% more efficient and up to 292 times faster when compared with that obtained using a similar work based on the sensitive-based gate sizing scheme.

Soft error tolerant design of combinational circuits based on a local logic substitution scheme

In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6].

A Scalable Solution to Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing

Current technology scaling trends aggressively increases the susceptibility of combinational circuit reliability to radiation-induced transient faults (which also known as soft errors). Various gate sizing techniques have been used to reduce soft error rate (SER) in the past, but their main drawback is that they are expensive in term of run time. These methods require changes to adapt to the large scale circuits. In this paper, an efficient circuit partitioning-based gate sizing method is presented, which significantly speeds up the gate sizing optimization process. In the proposed method, the circuit is divided into the topologically levelized small subcircuits by cone structures. Then, the subcircuits which are located in the same level are resized individually and independently. The subcircuit error probability (SEP) metric is introduced to evaluate the contribution of each subcircuit into the total circuit SER. The key idea of the proposed method is to evaluate the effects of each gate sizing on circuit reliability locally using SEP instead of global evaluation by the total circuit SER. Such evaluation results in speeding up the gate sizing optimization process. Experimental results show that the proposed approach is about 280× orders of magnitude faster than the sensitivity-based gate sizing approach [R. R. Rao, D. Blaauw, and D. Sylvester, “Soft error reduction in combinational logic using gate resizing and flipflop selection,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. , 2006, pp. 502–509] while it can achieve up to 45% reduction in circuit SER with less than 17% area overhead. This level of speed and efficiency makes the proposed approach a viable solution to mitigate the SER of very large combinational circuits used in industry.

Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations

Soft errors in combinational logic circuits are emerging as a significant reliability concern for nanoscale VLSI designs. This paper presents a novel sensitivity-based gate sizing methodology to reduce the soft error rate (SER) of combinational circuits in the presence of process variations. The proposed method is based on modeling the statistics of SER of the circuit gates as a random variable to formulate a statistical optimization problem. A backward traversing algorithm with capability for incremental analysis is developed for computing the distribution of circuit gates of SER random variables. We present a gate resizing algorithm in which the gates with the most contribution to the circuit SER are selected in a candidate set using a statistical ordering approach. The proposed algorithm trades off SER reduction and area overheads. The experimental results show that using the proposed methodology, the circuit statistical SER can be reduced by up to 56.4% compared with the 14.8% SER reduction of a circuit obtained using the worst case methodology at the expense of 10% area overhead under 10% process variation ratio. The results also show that the proposed method achieves about 40% more SER reduction compared with that obtained using closed-form analysis for statistical soft error rate estimation (CASSER), the most recently published similar work, in the same experimental conditions. Comparing the runtime of the proposed optimization algorithm with the optimization based on CASSER, it is observed that the proposed method is two orders of magnitude faster than CASSER due to its incremental analysis property.

Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs

As technology scaling increases embedded static random access memory bit-cell density, the number of soft errors due to radiation-induced multiple-bit upsets (MBUs) also increases. Traditionally, these errors have been addressed using a simple error correction code (ECC) combined with word interleaving. With continued scaling, however, errors beyond this setup begin to emerge. Although more powerful ECCs exist, they come at an increased overhead in terms of area and latency. Additionally, interleaving adds complexity to the system and may not always be feasible for the given architecture. In this brief, a set of double adjacent error correction (DAEC) codes is modified to provide triple adjacent error correction for a cost of zero additional check-bits over the code's DAEC equivalent, yielding a 2.25× reduction in bit-level soft error rate for a 22-nm MBU error channel model. MATLAB simulation and HDL synthesis results are included for standard 16- and 32-data-bit memory word sizes and compared against existing codes.

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.

Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment

Soft errors, which have been a significant concern in memories, are now a main factor in reliability degradation of logic circuits. This paper presents a power-planning-aware methodology using dual supply voltages for soft error hardening. Given a constraint on power overhead, our proposed framework can minimize the soft error rate (SER) of a circuit via selective voltage assignment. In the 70-nm predictive technology model, circuit SER can be reduced by 23% on top of SER-aware gate resizing. For power-planning awareness, a bi-partitioning technique based on a simplified version of the Fiduccia-Mattheyses (FM) algorithm is presented. The simplified FM-based partitioning refines the result of selective voltage assignment by decreasing the number of connections across voltage islands, while maintaining the SER reduction that has been accomplished.

Reliable Implementation on SRAM-based FPGA using Evolutionary Methods

The mitigation of Single Event Upset (SEU), in the implemented circuits on SRAM-based FPGAs is a crucial issue with increasing usage of such chips in aerospace applications. In this paper, three evolutionary methods have been developed to reduce Soft Error Rate (SER) of such circuits. The first two methods are based on Genetic Algorithm (GA) and Particle Swarm Optimization (PSO), and the other one is a co-evolutionary method which improves the convergence rate and cost of the former methods. The efficiency of these methods has been shown by comparing SER of implemented circuits using these methods with Versatile Place and Route (VPR) counterparts. More than 35% in SER reduction has been achieved for some MCNC benchmark circuits.

A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

Due to current technology scaling trends such as shrinking feature sizes and decreasing supply voltages, circuit reliability is becoming more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits as well. In this paper, we present a systematic and integrated methodology for circuit robustness to soft errors. The proposed soft error rate (SER) reduction framework, based on redundancy addition and removal (RAR), aims at eliminating those gates with large contribution to the overall SER. Several metrics and constraints are introduced to guide the RAR-based approach toward SER reduction. Furthermore, we integrate a resizing strategy into our framework, as post-RAR additive SER optimization. The strategy can identify most critical gates to be upsized and thereby, minimize area and power overheads while maintaining a high level of soft error robustness. Experimental results show that the proposed RAR-based framework can achieve up to 70% reduction in output failure probability. On average, about 23% SER reduction is obtained with less than 4% area overhead.

Output remapping technique for critical paths soft-error rate reduction

As technology scales, soft errors in deep submicron circuits have become a major reliability concern due to smaller node capacitances and lower supply voltages. It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. The authors proposed here an output remapping technique to reduce SER of critical paths. The SER reduction of our method ranges from 59.2 to 89.8%. This method does not introduce any delay penalty in most cases. The area/power overhead is limited as well. The output remapping method is based on the trade-off between SER and gate delay. The analysis shows that the width of the particle strike induced glitch scales down with technology scaling, which guarantees that output remapping technique works well along with technology scaling.

SERSim: a soft error rate simulator and a case study for a 32-bit OpenRisc 1200 microprocessor

Soft error is becoming increasingly important in the era of sub-100 nanometer very large scale integrated (VLSI) circuits. This article focuses on the impact of soft error on an OpenRisc 1200 CPU core. A C++ programming language based soft error analysis tool, with the name of SERSim, is created to perform a detailed exploration of this impact. The estimation error of SERSim ranges from 0.1% to 4.5%. With the help of SERSim, we find out that almost all the glitch widths are narrower than 200 ps in a 45 nm OpenRisc 1200 microprocessor circuit. This result is important for soft error rate reduction of VLSI circuits. The outputs of the multiplier of the OpenRisc 1200 microprocessor are found to be the most troublesome. Those outputs, which represent only 3% of the circuit outputs, produce more than half of the circuit bit error rate. A significant impact of performance requirements on circuit vulnerability to soft error is observed in our experiment. The difference helps us to analyse the estimation error of high-level soft error models.

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event transients (SETs) before they can be captured in latches or flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SET that can be suppressed. A TTF requires 6–14 transistors, making it an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-V DD and gate sizing is described. Simulation results for the 65 nm process technology indicate that a 17–48× reduction in the soft error rate can be achieved with this approach.

Signature-Based SER Analysis and Design of Logic Circuits

We explore the use of signatures, i.e., partial truth tables generated via bit-parallel functional simulation, during soft error analysis and logic synthesis. We first present a signature-based CAD framework that incorporates tools for the logic-level analysis of soft error rate (x) and for signature-based design for reliability (SiDeR). We observe that the soft error rate (SER) of a logic circuit is closely related to various testability parameters, such as signal observability and probability. We show that these parameters can be computed very efficiently (in linear time) by means of signatures. Consequently, AnSER evaluates logic masking two to three orders of magnitude faster than other SER evaluators while maintaining accuracy. AnSER can also compute SER efficiently in sequential circuits by approximating steady-state probabilities and sequential signal observabilities. In the second part of this paper, we incorporate AnSER into logic synthesis design flows aimed at reliable circuit design. SiDeR identifies and exploits redundancy already present in a circuit via signature comparison to decrease SER. We show that SiDeR reduces SER by 40% with only 13% area overhead. We also describe a second signature-based synthesis strategy that employs local rewriting to simultaneously improve area and decrease SER. This technique yields 13% reduction in SER with a 2% area decrease. We show that combining the two synthesis approaches can result in further area-reliability improvements.

Relevant metrics for evaluation of concurrent error detection schemes

Concurrent error detection (CED) schemes are becoming essential features in the design process as IC technologies progress into the nanoscale era. Soft error rate reduction has emerged as an important challenge and several works are dedicated to quantify the CED effective enhancement in systems reliability. However, none of them make a comprehensive description of the output events that can occur in such schemes. In this paper we propose a methodology to evaluate circuits with CED, including the time penalty as a relevant metric even in hardware redundancy techniques. Our experiments have shown that systems can reduce their throughput by half in multiple fault environments making the choice of the CED scheme strongly dependent on this analysis.

Modeling and Optimization for Soft-Error Reliability of Sequential Circuits

Due to reduction in device feature size and supply voltage, the sensitivity to radiation-induced transient faults of digital systems dramatically increases. In this paper, we present two approaches to evaluating the susceptibility of sequential circuits to soft errors. The first approach uses the Markov chain theory but can only provide steady-state behavior information. The second approach uses symbolic modeling based on binary decision diagrams/algebraic decision diagrams and circuit unrolling. The soft-error rate (SER) evaluation using this approach is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4% average error and up to 11 000x faster when compared to HSPICE detailed circuit simulation. The framework can be used for selective gate sizing targeting radiation hardening, leading up to 80% SER reduction when applied to a subset of ISCAS'89 benchmarks.

Quantifying the Reduction in Collected Charge and Soft Errors in the Presence of Guard Rings

Soft errors pose a major reliability threat to advanced electronic components and systems. Novel techniques are needed to mitigate the soft-error rate (SER) of integrated circuits (ICs), and in some cases, a combination of different mitigation techniques may be required for significant performance improvements. In this paper, an autonomous single-event-transient (SET) pulse-width characterization technique is used to quantify the effect of hardened-by-design structures, such as guard rings (GRs), in reducing the collected charge and SER of ICs. Experimental results obtained for a 0.35-mum technology show a reduced SET pulse-width for devices with GRs; the corresponding reduction in SER was estimated to be greater than 55% for technologies ranging from 0.35 mum to 70 nm.