A Scalable Solution to Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing

Abstract

Current technology scaling trends aggressively increases the susceptibility of combinational circuit reliability to radiation-induced transient faults (which also known as soft errors). Various gate sizing techniques have been used to reduce soft error rate (SER) in the past, but their main drawback is that they are expensive in term of run time. These methods require changes to adapt to the large scale circuits. In this paper, an efficient circuit partitioning-based gate sizing method is presented, which significantly speeds up the gate sizing optimization process. In the proposed method, the circuit is divided into the topologically levelized small subcircuits by cone structures. Then, the subcircuits which are located in the same level are resized individually and independently. The subcircuit error probability (SEP) metric is introduced to evaluate the contribution of each subcircuit into the total circuit SER. The key idea of the proposed method is to evaluate the effects of each gate sizing on circuit reliability locally using SEP instead of global evaluation by the total circuit SER. Such evaluation results in speeding up the gate sizing optimization process. Experimental results show that the proposed approach is about 280× orders of magnitude faster than the sensitivity-based gate sizing approach [R. R. Rao, D. Blaauw, and D. Sylvester, “Soft error reduction in combinational logic using gate resizing and flipflop selection,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. , 2006, pp. 502–509] while it can achieve up to 45% reduction in circuit SER with less than 17% area overhead. This level of speed and efficiency makes the proposed approach a viable solution to mitigate the SER of very large combinational circuits used in industry.