General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework

Abstract

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100%<; area overhead <; 200%, the solutions of MIX have lower SER (SER reduction >81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).