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https://doi.org/10.6843/nthu.2009.00645
Copy DOIPublication Date: Jan 1, 2009 |
With the advances of semiconductor technology, the transistor size has been scaled down. This shrinkage makes the circuits more susceptible to the soft error, which is a wrong signal or data latched by storage elements. Thus, Soft Error Rate (SER) reduction has become an important issue recently. In this work, we propose two methods for minimizing this SER based on a circuit restructuring technique, IRredundancy Removal and Addition. Our first method is to rewire the higher SER gates while the second one is to restructure the subcircuits having higher soft error impacts. Experiential results show that the first method presents a reduction of 19.6\% SER and 9.9\% area on a set of ISCAS'85 and MCNC benchmarks on average. The second method gets 23.7\% soft error rate reduction with 9.6\% area overhead. By combining these two methods, we can rise the ratio of SER decreasing rate to area increasing rate up to 6.77. This ratio indicates our approach can reduce the SER within a small cost.
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