Abstract
The effects of soft error in combinational logics are challenged by decreasing the feature size of transistors in nanoscale technologies. Moreover, the single event transients (SETs) caused by particle strikes, manifesting multiple event transients (METs), are expectable, as well. Coping with this problem is the end of CLEAR using a cross-layer method as an effective way to mitigate the rate of double event transients (DETs) in combinational logic. First, an algorithm is proposed based on local displacements and linear programming (LP) optimization problem, which locates the cells in the best way from the DETs point of view. Next, two hardening methods are proposed based on resizing and fault masking. Finally, one of these two methods is applied to the aforesaid algorithm results, modified layout, considering the given design parameters. Experimental studies reveal a reduction of 42.9% on average in DETs rate, which can be improved up to 51.1% and 68.9% by applying two aforementioned hardening methods with some negligible overhead.
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