Design of a low-area hardware architecture to predict early signs of sudden cardiac arrests

Abstract

Sudden cardiac arrest (SCA) results in an unexpected and untimely death within minutes, and its early prediction can alert cardiac patients to a timely medical diagnosis. To detect early symptoms of an SCA, the detection and classification of ventricular tachycardias (VT) are of utmost importance. In this work, a low-area yet highly accurate hardware architecture for VT classification is proposed based on the detection of premature ventricular contraction (PVC) beats. After pre-processing of the ECG signals using a wavelet-based pre-processing unit, a characteristics-matching algorithm is used to detect the PVC beats, and a low-complexity adaptive decision-based logic classifier is used to classify them into four types of VTs, namely monomorphic, polymorphic, non-sustained VT (NSVT), and sustained VT (SVT). FPGA verification of the hardware architecture for the VT classifier using the Nexys 4 DDR Artix-7 board utilizes 10.4 % of the total available resources and displays the type of VT and the number of PVCs detected to help in determining the severity of SCA and the need for medical attention. The ASIC implementation of the proposed PVC-based VT classification using the SCL 180 nm CMOS technology results in an area overhead of 0.02 mm2 and a power consumption of 3.47 μW for a high accuracy rate of 98.2 %. When compared to the existing CA detection systems for wearable devices, the proposed one consumes the least area while achieving high detection rates.