Abstract

By decreasing transistors feature size in nanoscale technology, the effect of soft error on combinational circuits has become a challenging problem as the particle strikes may lead to not only single event transients (SETs) but also multiple event transients (METs). In this paper, a cross-layer method is employed in order to achieve an effective way to reduce the occurrence rate of METs in combinational circuits. In the proposed method, at first, the desired circuit is synthesized and the sensitivity of each pair of cells with respect to METs is investigated through simulating and taking into account all three masking effects (electrical, logical, and temporal effects) at the gate level. Then, the circuit is placed and routed with the use of commercial CAD tools. Afterward, a cross-layer method is presented to estimate the soft error rate with respect to layout effect. Finally, by introducing a linear optimization problem, the unused space available on each row of the layout is distributed in the best way from the METs point of view. As a result, the multiple fault rate has been reduced 42.9% on average without having any area or performance overhead.

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