Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment

Abstract

Soft errors, which have been a significant concern in memories, are now a main factor in reliability degradation of logic circuits. This paper presents a power-planning-aware methodology using dual supply voltages for soft error hardening. Given a constraint on power overhead, our proposed framework can minimize the soft error rate (SER) of a circuit via selective voltage assignment. In the 70-nm predictive technology model, circuit SER can be reduced by 23% on top of SER-aware gate resizing. For power-planning awareness, a bi-partitioning technique based on a simplified version of the Fiduccia-Mattheyses (FM) algorithm is presented. The simplified FM-based partitioning refines the result of selective voltage assignment by decreasing the number of connections across voltage islands, while maintaining the SER reduction that has been accomplished.