Output remapping technique for critical paths soft-error rate reduction

Abstract

As technology scales, soft errors in deep submicron circuits have become a major reliability concern due to smaller node capacitances and lower supply voltages. It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. The authors proposed here an output remapping technique to reduce SER of critical paths. The SER reduction of our method ranges from 59.2 to 89.8%. This method does not introduce any delay penalty in most cases. The area/power overhead is limited as well. The output remapping method is based on the trade-off between SER and gate delay. The analysis shows that the width of the particle strike induced glitch scales down with technology scaling, which guarantees that output remapping technique works well along with technology scaling.