Soft-core Processor Research Articles

ANFIS Analysis of Wireless Sensor Data with FPGA

Applications related with WSNs may include thousands of separate sensor nodes, production and control data for different industrial sectors. It is important to manage these applications, monitor the network and reprogram the nodes to avoid operational problems. In this study, we propose a smart wireless sensor network using a reconfigurable embedded system of Field-Programmable Gate Arrays (FPGAs) with a soft-core processor. This processor can be programmed dynamically and synthesized to implement the preprocessing of sensed data by ensemble Hybrid Neuro-Fuzzy algorithms such as Adaptive Neuro-Fuzzy Inference System (ANFIS). The first part of the proposed work is based on Matlab software to develop and train the ANFIS algorithm. Two different types of data sets (temperature and humidity) downloaded from Internet have been used in order to make a comparison between the Matlab Toolbox and modified ANFIS algorithm with momentum factor. The results obtained in this study have shown that the modified ANFIS algorithm is the convenient choice in terms of speed, accuracy.

Performance Estimation of Scheduling Algorithms on Microblaze Softcore Processor

Performance Estimation of Scheduling Algorithms on Microblaze Softcore Processor

FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

Design of FPGA based NIOS-II Soft Core Processor for a wearable Tele Cardiac System

Design of FPGA based NIOS-II Soft Core Processor for a wearable Tele Cardiac System

Field Programmable Gate Array Softcore Processors Optimised for Digital Signal Processing Applications

The benefits of adding explicit DSP operation support to an FPGA-based softcore processor are examined. An experimental DSP processor has been designed, implemented, simulated, and verified on a Xilinx Virtex-5 XC5VSX50T FPGA chip. An initial very simple architecture is upgraded with different supporting hardware to enhance the processor's performance in execution of DSP applications. These hardware enhancement techniques include a specialist execution unit, modification to the memory architecture, adding an extra address control unit, upgrading with more active addressing modes, and extending the instruction set with zero-overhead looping support. These enhancements reduce the number of instructions used in the inner loop of convolution-based DSP algorithms to a single instruction. By using these proposed enhancement techniques, the overall performance was improved by an average of 9 times (800% improvement) in FIR Filter and Matrix Multiplication benchmark DSP applications. The overall area increased by about 1.41 times (41% extra cost). Using in-built DSP blocks in the FPGA instead of logic blocks to implement the arithmetic unit of the processor reduced the power consumption by 14% from 840 mW to 725 mW.

A Hardware Implementation of the Levinson Routine in a Radio Detector of Cosmic Rays to Improve a Suppression of the Nonstationary RFI

The radio detector system for ultrahigh-energy cosmic rays in the Pierre Auger Observatory operates in the frequency range 30–80 MHz, which is often contaminated by human-made radio-frequency interferences (RFIs). Several filters were used to suppress the RFI: based on the FFT, an IIR notch filter, and an FIR filter based on the linear prediction. The last refreshes the FIR coefficients calculating either in the external ARM processor, internal soft-core NIOS processor implemented inside the field programmable gate aray (FPGA), or hard-core embedded processors [based on Integrated ARM Cortex-A9800 MHz Hardcore Processor System (HPS)] being a silicon part of the FPGA chip. Refreshment times significantly depend on the type of calculation process. For a stationary RFI, the FIR coefficients can be refreshed each minute or rarer. However, an efficient suppression of nonstationary short-term contaminations requires a much faster response. Calculations of FIR coefficients in an external Voipac PXA270M ARM processor take 1–2 s, by the soft-core virtual NIOS processor on the level of hundreds of milliseconds. The HPS allows a reduction of the refreshment time to ~20 ms (for a 32-stage FIR filter). A symmetry of covariance matrix allows one to use the much faster Levinson procedure instead of typical Gauss routine for solving a set of linear equations of time. A hardware implementation of this procedure inside the FPGA fabric as a specialized $\mu \text{C}$ (with 100-MHz clock) requires only ~53 800 clock cycles. We used 64- or 48-b floating-point representations to calculate FIR coefficients. Resources occupation is relatively high, as the design was optimized for a maximal register performance. However, the RFI suppression is very efficient. We expect a significant suppression of even a short-term nonstationary RFI.

Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture

The rising demands for computational performance are a permanent trend in our increasingly digital world. Consistently addressing this trend poses a challenge for every embedded processor system. This paper proposes the use of reconfigurable processor architectures to increase “on demand” processing performance while running a specific target application. The reconfiguration is used to interchange specialized co-processors attached to a static soft-core processor during run-time. Different self-optimization software–hardware substitution mechanisms, inspired by the field of organic computing, are implemented and evaluated using two different synthetic benchmarks and an exemplary application from the field of parallel robotics. An efficient self-optimization can be reached by combining a speed-up-based replacement strategy for scheduling the reconfigurable co-processors and a least mean square optimization algorithm without requiring any a-priori application profiling. For a reduced number of reconfigurable co-processors, the results show that the proposed software–hardware reconfiguration strategy provides, in general, better trade-offs between the required hardware resources and performance improvement when compared to the equivalent soft-core processor with the same number of static co-processors.

Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors

Abstract The paper presents three embedded soft-core processor architectures, developed by the authors to be easily implementable while yielding low digital resource usage. These architectures will be compared and contrasted between each-other by introducing a special testing method, based on control algorithm implementations. For reference, the same testing and comparison has been implemented on a well established architecture, too, on the Xilinx PicoBlaze processor. Measurement results and application suggestion are given in the concluding section.

MIPSfpga: using a commercial MIPS soft‐core in computer architecture education

In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS

Objective: The prospective need of SIMD (Single Instruction and Multiple Data) applications like video and image processing in single system requires greater flexibility in computation to deliver high quality real time data. This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement by data level parallelism executing SIMD instruction simultaneously in HPRC (High Performance Reconfigurable Computing) at reduced resource utilization through RRF (Reconfigurable Register File) with multiple core functionalities. This work aims at analyzing the functionality of the reconfigurable architecture, by illustrating the implementation of two different image processing operations such as image convolution and image quality improvement. The MAC (Multiply-Accumulate) unit of ROR1200 used to perform image convolution and execution unit with HPRC is used for image quality improvement.Result: With parallel execution in multi-core, the proposed processor improves image quality by doubling the frame rate up-to 60 fps (frames per second) with peak power consumption of 400mWatt. Thus the processor gives a significant computational cost of 12ms with a refresh rate of 60Hz and 1.29ns of MAC critical path delay.Conclusion:This FPGA based processor becomes a feasible solution for portable embedded SIMD based applications which need high performance at reduced power consumptions

A simulation framework for code-level energy estimation of embedded soft-core processors

This contribution presents a simulation framework for code-level energy estimation of open-source MIPS-R2000, LEON3, and openMSP430 embedded soft-core processors. The method proposed in this work is generic and can be extended to other processors and architectures. The framework consists of two modules as follows. (i) An instruction-level power estimator module that estimates the average power consumption of individual machine instructions simulated using gate-level net-lists of the target processors. This module is used to create instruction-level power consumption databases of the target processor. (ii) A high-level energy estimation module parses the assembly code written for a target processor and gives the estimated energy consumed while taking the inherent data and control dependencies into consideration. Our proposed framework, therefore, provides rapid offline code-level energy estimation using simulations and avoids the low-level hardware estimation overheads. The energy estimation time efficiency of our proposed methodology is evaluated by using different benchmarks against the results of other existing energy estimation frameworks, such as SoftExplorer, TLM with the ISS-based simulation tool, SimplePower/WATTCH, and EPEM. These results indicate that our proposed framework is roughly one to two orders of magnitude faster in energy estimation. From the accuracy perspective, our energy estimations lie, on average, within 2% of those obtained from WATTCH. The proposed tool is especially useful in estimating the algorithmic energy efficiency of various codes targeted at low/moderate-end embedded systems, such as wireless sensor network nodes.

New design of the PV panel control system using FPGA-based MPSoC

The photovoltaic (PV) systems require parallel processing capabilities for tracking both sun and maximum power point (MPP). This paper presents a new approach of using the field programmable gate array (FPGA) as a multiprocessor system on a chip (MPSoC) to maximize the PV system performance. The FPGA based subsystem is used for controlling a single axis sun tracker and the maximum power point tracking (MPPT) using three soft-core processors. The sun tracking control scheme is based on a fuzzy logic control (FLC) algorithm guided by a set of time-based solar angle equations. The MPPT is employed using the variable step-size incremental conductance (INC) method. The main advantage of the proposed architecture is its ability to handle simultaneous tasks that require large memory size and floating point computations. Due to its flexibility the user can add more soft-cores to reduce the software complexity and increase the processing speed. The performance of a 50W PV panel is tested experimentally and theoretically using the proposed tracking system. Results have shown graphically that the sun tracking achieves a small settling time with zero overshoot. Also, increasing the number of processors reduces the settling time of the sun tracking and MPPT. The combination increases the system output power with about 10.1%.

Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths

Viterbi algorithm is widely used in communication systems to efficiently decode the convolutional codes. This algorithm is used in many applications including cellular and satellite communication systems. Moreover, Serializer-deserializers (SERDESs) having critical latency constraint also use viterbi algorithm for hardware implementation. We present the integration of a mixed hardware/software viterbi accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. Later we investigate the performance of viterbi accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the viterbi accelerated Microblaze soft-core embedded processor datapath is three times more cycle and energy efficient than a datapath lacking a viterbi accelerator unit. This acceleration is achieved at the cost of some area overhead.

Benefits of Complementary SEU Mitigation for the LEON3 Soft Processor on SRAM-Based FPGAs

A variety of mitigation techniques have been demonstrated to reduce the sensitivity of FPGA designs to soft errors. Without mitigation, SEUs can cause failure by altering the logic, routing, and state of a design operating on an SRAM-based FPGA. Various combinations of SEU mitigation and repair techniques are applied to the LEON3 soft-core processor to study the effects and complementary nature of each technique. This work focuses on Triple modular redundancy (TMR), configuration memory (CRAM) scrubbing, and internal block memory (BRAM) scrubbing. All mitigation methods demonstrate some improvement in both fault injection and neutron radiation testing. Results in this paper show complementary SEU mitigation techniques working together to improve fault-tolerance. The results also suggest that fault injection can be a good way to estimate the cross section of a design before going to a radiation test. TMR with CRAM scrubbing demonstrates a $27\times $ improvement whereas TMR with both CRAM and BRAM scrubbing demonstrates approximately a $50\times $ improvement.

A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA

In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and fault injection in an incremental manner. The error mitigation approach combines the use of SEC/DED codes for memories, a hardware monitor to detect control-flow errors, software-based techniques to detect data errors and configuration memory scrubbing with repair to avoid error accumulation. The proposed solution can significantly improve fault tolerance and can be fully embedded in a low-end FPGA, with reduced overhead and low intrusiveness.

Improved reconfigurable hyper-pipeline soft-core processor on FPGA for SIMD

Reconfiguration is a powerful computational model in which the processors can be changed dynamically during the execution phase of the system. This paper presents dynamic reconfigurable register file allocation in hyper pipelined OR1200 (Open RISC) for single instruction multiple data (SIMD). The OR1200 instantly reconfigures the actual register file to the reconfigurable register file according to the requirement of the application. The unused general purpose registers obtained during the reconfiguration process can be used for hyper pipelining technique which improves overall performance of the single core processor system. Thus releasing the unused register reduces the power consumption and increases the execution speed of OR1200. This proposed reconfigurable technique is implemented using Verilog and it is tested using MediaBench multimedia benchmark dataset which ensures reduced register utilisation of 16.80% for multimedia dataset and power reduction up to 72.7% with reconfigurable modules. The proposed technique is configured in Virtex-6 field programmable gate array (FPGA) and results are analysed with the existing and proposed reconfigured OR1200.

Improved reconfigurable hyper-pipeline soft-core processor on FPGA for SIMD

Improved reconfigurable hyper-pipeline soft-core processor on FPGA for SIMD

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor.

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation.

A Hardware/Software Prototype of EEG-based BCI System for Home Device Control

This paper presents a design exploration of a new EEG-based embedded system for home devices control. Two main issues are addressed in this work: the first one consists of an adaptive filter design to increase the classification accuracy for motor imagery. The second issue deals with the design of an efficient hardware/software embedded architeclture integrating the entire EEG signal processing chain. In this embedded system organization, the pre-processing techniques, which are time consuming, are integrated as hardware accelerators. The remaining blocks (Intellectual Properties - IP) are developed as embedded-software running on an embedded soft-core processor. The pre-processing step is designed to be self-adjusted according to the intrinsic characteristics of each subject. The feature extraction process uses the Common Spatial Pattern (CSP) as a filter due to its effectiveness to extract the ERD/ERS (Event-Related Desynchronization/ Synchronization) effect, where the classifier is based on the Mahalanobis distance. The advantage of the proposed system lies in its simplicity and short processing time while maintaining a high performance in term of classification accuracy. A prototype of the embedded system has been implemented on an Altera FPGA-based platform (Stratix-IV). It is shown that the proposed architecture can effectively extract discriminative features for motor imagery with a maximum frequency of 150 MHz. The proposed system was validated on EEG data of twelve subjects from the BCI competition data sets. The prototype performs a fast classification within time delay of 0.399 second per trial, an accuracy average of 94.47 %, an average transfer rate over all subjects of 20.74 bits/min. The estimated power consumption of the proposed system is around 1.067 Watt (based on an integrated tool-power analysis of Altera corporation).

FPGA-Based Soft-Core Processors for Image Processing Applications

With security and surveillance, there is an increasing need to process image data efficiently and effectively either at source or in a large data network. Whilst a Field-Programmable Gate Array has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and verification. The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA implementations whilst reducing design time. The paper also reports some preliminary progress on the design flow to program the structure. An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification and debugging steps associated with conventional FPGA implementations.