Abstract
Viterbi algorithm is widely used in communication systems to efficiently decode the convolutional codes. This algorithm is used in many applications including cellular and satellite communication systems. Moreover, Serializer-deserializers (SERDESs) having critical latency constraint also use viterbi algorithm for hardware implementation. We present the integration of a mixed hardware/software viterbi accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. Later we investigate the performance of viterbi accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the viterbi accelerated Microblaze soft-core embedded processor datapath is three times more cycle and energy efficient than a datapath lacking a viterbi accelerator unit. This acceleration is achieved at the cost of some area overhead.
Highlights
Channel coding is used in wireless communication systems for reliable data transfer over noise prone communication channels
The viterbi decoder is suitable in wireless communication systems in which the transmitted signals are corrupted by additive white Gaussian noise [6]
B represents each metric table entry bits and n represent number of output bits. This initial implementation of viterbi decoder with different constraint lengths was synthesized on 7vx485tffg1157-3 Virtex-7 FPGA device which is based on a 28nm technology
Summary
Channel coding is used in wireless communication systems for reliable data transfer over noise prone communication channels. The viterbi decoder can be implemented more efficiently in dedicated hardware which will require few clock cycles at the cost of flexibility. Different hardware modules like USB, Ethernet, TCP/IP, CRC and CAN protocol are included in modern embedded processors [7], [8], [9] to speedup certain parts of application in areas like signal processing, communication and control systems. This provides effective use of viterbi accelerator in programming systems where a series of viterbi decoding is required to be computed
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