Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture

Abstract

The rising demands for computational performance are a permanent trend in our increasingly digital world. Consistently addressing this trend poses a challenge for every embedded processor system. This paper proposes the use of reconfigurable processor architectures to increase “on demand” processing performance while running a specific target application. The reconfiguration is used to interchange specialized co-processors attached to a static soft-core processor during run-time. Different self-optimization software–hardware substitution mechanisms, inspired by the field of organic computing, are implemented and evaluated using two different synthetic benchmarks and an exemplary application from the field of parallel robotics. An efficient self-optimization can be reached by combining a speed-up-based replacement strategy for scheduling the reconfigurable co-processors and a least mean square optimization algorithm without requiring any a-priori application profiling. For a reduced number of reconfigurable co-processors, the results show that the proposed software–hardware reconfiguration strategy provides, in general, better trade-offs between the required hardware resources and performance improvement when compared to the equivalent soft-core processor with the same number of static co-processors.