Abstract
Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. The trend for soft-core processors, as well as mainstream CPUs (central processing units), leads to multi-core architectures. Both the necessary memory architectures and the compilers play an important role in this process. In this paper, a novel method that aims at minimizing the necessary memory resources on the FPGA while maximizing the processing speed of any given algorithm is described. In the first step, an application-specializable multi-soft-core processor architecture is presented that is capable of solving problems while adhering to hard real-time deadlines. Its special architecture and other necessary features are discussed. Furthermore, a method for the generation of optimized machine code for each processor core as well as hard real-time compatible deadlock handling mechanisms are presented. Selected algorithms are implemented to demonstrate the functionality and efficiency of the realized approach for different configurations of the multi-soft-core processor architecture.
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