Abstract
This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation.
Highlights
Computer vision (CV) has many possible utilizations and is one of the fastest growing research areas these days
This paper describes a real time system to recognize a predefined marker with known geometries and calculate the pose of the detected markers in the frame
System experiments and simulations where carried out using an Altera DE2-115 board powered by a Cyclon IVE field-programmable gate array (FPGA) chip
Summary
Computer vision (CV) has many possible utilizations and is one of the fastest growing research areas these days. Different views of an object, surface reflections and noise from image sensors are the challenging questions with which one has to deal when it comes to pose estimation and optical object detection The solution to these problems to some extent can be achieved thanks to the use of SIFT or SURP algorithms as they compute the point features, which are invariant towards scaling and rotation [5,6]. Low-cost sensors have been discussed in [7] They have accelerated block matching motion estimation techniques using the Altera C2H. The second subsystem is a Nios II soft core processor based on RISC architecture Using this processor, the Coplanar PosIT algorithm can be implemented.
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