整合SDRAM控制器、主僕式矽智財、與SoC匯流排分析儀之系統晶片設計架構

Abstract

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.