Formal verification for SoC security

Abstract

The wide adoption of third -party hardware intellectual property (IP) cores, including those from untrusted vendors, has raised security concerns for system designers and end users. Existing approaches to ensure the trustworthiness of individual IPs rarely consider the entire system -on -chip (SoC) design, especially the IP interactions through SoC bus. These methods can hardly identify malicious logic (or design fl aws) distributed in multiple IPs, whereas individual IPs fulfill security properties and can pass the security testing/verification. One possible solution is to treat the SoC as one IP core and try to verify security properties of the entire design. This method, however, suffers from scalability issues due to the large size of SoC designs with multiple IP cores integrated. In this chapter, we present a scalable SoC bus verification framework trying to verify the security properties of SoC bus implementation where the bus protocol plays the role of the golden reference. More specifically, finite state machine (FSM) models will be constructed from the bus implementation, and the trustworthiness will be verified based on the property set derived from the bus protocol and potential security threats. Along with IP level formal verification solutions, the proposed framework can help one to ensure the security of large-scale SoCs. Experimental results on ARM advanced micro -controller bus architecture (AMBA) bus demonstrate that our approach is applicable and scalable to prevent information leakage and denial -of -service (DoS) attack by verifying security properties.