Validation of Open Core Protocol by Exploiting Design Framework Using System Verilog and UVM

Abstract

Today’s scenario of semiconductor technology is a tremendous innovation; it includes a large number of intellectual property (IP) cores, interconnects, or buses in system on chip (SOC) design and based upon the necessity its complexity keeps on increasing. Hence, for the communication between these IP cores, a standard protocol is developed. The necessity of IP reuse, abridging the design time and the complexity makes large-scale SOC more challenging in order to endorse IP core reusability for SOC designs. An efficient non-proprietary protocol for communication between IP cores is open core protocol (OCP). OCP comes under socket-based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.