Smart Power ICs Research Articles

Development of 4H-SiC LJFET-Based Power IC

A novel lateral junction field-effect transistor (JFET)-based power IC technology in 4H-SiC is presented in detail covering device and circuit design, fabrication, and characterization. The optimal reduced surface field design for the lateral power JFET has been carried out and implemented in the IC fabrication. Since this technology has great promise at high temperatures, the temperature dependences (from room temperature to 300degC) of the threshold voltage, transconductance, resistance, and electron mobility have been fully characterized. Advantages of the SiC vertical-channel lateral JFET (VC-LJFET) technology, such as lower output capacitance (Coss) for lateral power JFETs and adjustable threshold voltages at mask design level, are also discussed. Finally, a monolithic power IC chip integrating a power lateral JFET with its low-voltage buffers is presented, which demonstrated megahertz switching at a power level of 270 W. The successful development of the VC-LJFET technology should hasten the introduction of SiC smart power ICs and eventually the system-on-a-chip applications in harsh environments.

Scalable High Voltage CMOS technology for Smart Power and sensor applications

Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded non-volatile memory. In this work we propose a new 0.35 µm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 µm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 °C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM/Flash technology is shown. We also provide first verification results of the scalability of the proposed 0.35 µm HVCMOS technology to 0.18 µm and beyond as well as to currents of up to 8 A.

Small signal modelling of Smart power IC

A method of small signal modelling for the Smart power IC is presented. The method is based on the IC's typical operational characteristics and small signal frequency response data. Using the least square identification, the IC's dynamic model, which was expressed as the transfer function, was synthesised from the gain and phase data from the experiment were obtained. The effectiveness and practicality of the method were verified through experiments.

Modeling Lateral Parasitic Transistors in Smart Power ICs

Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic transistors have to be included into a postlayout simulation. A methodology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behavior and accuracy of the model has been found

Substrate Majority Carrier-Induced NLDMOSFET Failure and Its Prevention in Advanced Smart Power IC Technologies

This paper discusses substrate majority carrier conduction and prevention for an n-type lateral double diffused MOSFET (NLDMOSFET) device in Smart Power IC technologies. Substrate majority carrier current poses severe electrical and thermal stress for NLDMOSFET devices and causes many system integration issues for advanced Smart Power IC technologies. A single- and multi-iso isolated NLDMOSFET is proposed and experimentally verified to eliminate the problem. Tradeoff between device size, safe operating area (SOA), substrate current, and NLDMOSFET-device power dissipation has been studied. Detailed analysis of device SOA for conventional and isolated devices and techniques to improve the device SOA has also been provided

Potentialities of substrate-thinning technique to control minority carrier injection in smart power IC's

This paper deals with the evaluation of a substrate-thinning technique as a way to control the substrate current issues. A test structure has been realized on a Smart Power Technology. Comprehension of the phenomena has been validated thanks to TCAD simulation. This technique was then applied to a commercial IC and the authors show that they succeeded to reduce by one decade the collected current on a victim, although the IC has already been optimized with classical solutions.

Transient blocking characteristics of highly efficient junction isolations based on standard CMOS process

This paper investigates the performance of single and multiple junction isolation structures for smart power IC’s with regards to transient carrier injection. Both, single and multiple isolation structures are produced using a standard CMOS process all using the same surface area. The devices are based on different active junction isolation principles and it is shown that combinations of these devices can significantly improve the blocking characteristics of the isolation without an increase in surface area. It is shown that the transient current rejection of the devices is markedly different from their dc blocking characteristics. Considerations for the design of efficient isolation structures are discussed.

A new Lateral Trench Electrode IGBT with a p+ diverter

A new Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) with a p+ diverter was proposed and fabricated to improve the electrical characteristics of the conventional LTIGBT. The p+ diverter was placed between anode and cathode electrodes. Because the p+ diverter region of the proposed device was enclosed in a trench oxide layer, the electric field centered in the trench-oxide layer, and the punch through breakdown of LTEIGBT with p+ diverter occurred at the high breakdown voltage. Therefore, the p+ diverter of the proposed LTIGBT didn’t relate to breakdown voltage in a different way the conventional LTIGBT. As a result of device simulation, the electrical characteristics of the proposed LTEIGBT including latching current density, breakdown voltage and switching speed were superior to conventional devices. After simulation was finished, we fabricated and analyzed the proposed LTEIGBT with a p+ diverter. The maximum current of the proposed device and conventional device were 90 and 70 mA, respectively. Therefore, the proposed LTEIGBT with a p+ diverter is an effective device for smart power IC.

A New Lateral Trench Electrode Insulated Gate Bipolar Transistor with p+ Diverter for Superior Electrical Characteristics

A new lateral trench electrode insulated gate bipolar transistor (LTEIGBT) with a p+ diverter was proposed and fabricated to improve the electrical characteristics of the conventional LTIGBT. The p+ diverter was placed between anode and cathode electrodes. Because the p+ diverter region of the proposed device was an enclosed trench oxide layer, the electric field centered on the trench oxide layer and the punch-through breakdown of the LTEIGBT with a p+ diverter was occurred at a high. Therefore, the p+ diverter of the proposed LTIGBT was not related to the breakdown voltage in contrast to that of the conventional LTIGBT. As a result of device simulation, the electrical characteristics of the proposed LTEIGBT including latching current density, breakdown voltage and switching speed were superior to those of the conventional LIGBTs. After simulation, we fabricated and analyzed the proposed LTEIGBT with a p+ diverter. The maximum currents of the proposed and conventional LTIGBTs were 90 mA and 70 mA, respectively. Therefore, the proposed LTEIGBT with a p+ diverter is an effective device for a smart power IC.

The Fabrication and Experimental Results of a New Lateral Trench Electrode IGBT with a p+ Diverter

A new Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) with a p+ diverter was proposed and fabricated to improve the electrical characteristics of the conventional LTIGBT. The p+ diverter was placed between anode and cathode electrodes. Because the p+ diverter region of the proposed device was enclosed trench oxide layer, the electric field centered trench-oxide layer, and punch through breakdown of LTEIGBT with p+ diverter was occurred at the high breakdown voltage. Therefore, the p+ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. As a results of device simulation, the electrical characteristics of the proposed LTEIGBT including latching current density, breakdown voltage and switching speed was superior to conventional devices. After simulation was finished, we fabricated and analyzed the proposed LTEIGBT with a p+ diverter. The maximum current of the proposed device and conventional device were 90 mA and 70 mA, respectively. Therefore, The proposed LTEIGBT with a p+ diverter is effective device for smart power IC.

A novel over-voltage protection method for 600V SPIC

A novel over-voltage protection method for 600V SPIC (Smart Power IC) is proposed in this paper. The combining FFLRs (Floating Field Limiting Rings) system is designed to be a voltage detector. The detector’s voltage can turn off the switch of the APFC (Active Power Factor Correction) circuit and the bus voltage would fall from 600VDC to 300VDC, so the SPIC and power devices can be protected. The advantages of this design are that the total protection circuits are integrated in SPIC and technologically compatible with CMOS or BCD(Bipolar-CMOS-DMOS) technology.

A robust smart power bandgap reference circuit for use in an automotive environment

In junction-isolated smart power technologies, negative voltages at the drain terminal of a power DMOS lead to minority carrier injection into the substrate. This can cause malfunction of sensitive circuits such as bandgap references and may subsequently lead to severe functional failures of the device. Furthermore, in smart power ICs, very high chip temperatures can occur due to excessive power dissipation on- or off-chip in fault conditions. In such cases, the operation of a bandgap reference must be guaranteed to ensure safe shutdown of the device even at excessive chip temperatures. In this paper, a robust bandgap circuit for the use in smart power ICs is presented. It is insensitive to minority carrier injection into the substrate and operates reliably up to temperatures of 260/spl deg/C.

Automatic 2-D and 3-D simulation of parasitic structures in smart-power integrated circuits

A new method to efficiently describe parasitic bipolar structures in junction-isolated smart-power ICs is reported. Both two- and three-dimensional situations are tackled. An automatic simulation code for calculating the parasitic currents injected into the substrate by power devices, which may endanger the functioning of the signal-processing circuits, has been developed. Also, a Java graphical interface has been implemented with the aim of automatically managing the mixed circuit-device simulation. Examples of applications are given with reference to BCD5 technology.

Experimental and theoretical analysis of energy capability of RESURF LDMOSFETs and its correlation with static electrical safe operating area (SOA)

Thermal and electrical destruction of 55 V single and double reduced surface field (RESURF) lateral double-diffused MOSFETs (LDMOSFETs) in smart power ICs are investigated by experiments, simulations, and theoretical modeling. Static safe operating area (SOA) and single pulse dynamic SOA (energy capability) have been studied and correlated. Single RESURF device failure and hence the energy capability is controlled by electrical phenomenon for drain to source voltage near breakdown voltages, whereas the energy capability of the double RESURF device is shown to be controlled by thermal phenomenon for voltage ranges up to about 5 V below the breakdown voltage. Measured energy capability data have been used to obtain critical temperatures for device failure, which decreases with an increase in drain to source voltage. We have empirically shown using experimental data that if the dynamic SOA of the device comes within about 2-5/spl times/ of the static SOA boundary, the device failure is strongly influenced by avalanche multiplication. An analytical model based on Green's function formulation is derived and proposed which can predict energy capability of LDMOSFETs for a wide range of device geometry. The calculated data show excellent matching with the measurements and are within /spl plusmn/10%. A new technique of distributing power within a device by applying less power at the center and more at the edges is proposed, which realizes significant improvement in energy capability by optimizing the temperature distribution within the device.

Improved latch-up immunity in junction-isolated smart power ICs with unbiased guard ring

The performance of the unbiased guard ring structure is measured and the effects of high current, emitter area, and layout of unbiased guard rings are reported and explained. Measurements show a reduction in parasitic gain by up to six orders of magnitude, while also avoiding the cross talk and power consumption of biased rings. A comparative analysis of unbiased guard ring with biased guard ring shows up to 100 times better performance at low current levels. A modification to the unbiased guard ring is also implemented and successfully tested which shows an increase in the current handling capability of the structure by an order of magnitude.

Power capability limits of power MOSFET devices

With technology progression, power capability becomes a more critical concern in optimizing power device designs in various smart power IC applications. Interaction between the electrical and thermal entities is essential in understanding the power capability limit of the semiconductor devices in both transient and steady-state operations. This paper reports the fundamental mechanisms of the electrical–thermal coupling process during power dissipation and the characteristics of the power capability limits of the power MOSFET devices from the scope of intrinsic and extrinsic factors that affect the power capability. An electrothermally driven snapback breakdown is discussed in detail to investigate the physical mechanism of the power capability limits of an LDMOS power transistor. Both simulation and experimental results are in good agreement, indicating that the electrothermal snapback breakdown would occur at lower junction temperature than the intrinsic junction temperature.

Substrate potential shift due to parasitic minority carrier injection in smart-power ICs: measurements and full-chip 3D device simulation

Substrate current injection effects are one of the major risks for smart-power IC functionality, often leading to redesigns. Smart-power ICs for motor control consist of four power transistors in H-bridge configuration and the controlling circuitry on a single chip. During switching of the power stages driving an inductive load (e.g. a motor), parasitic bipolar transistors turn on and inject electrons and holes into the substrate. This leads to a substrate potential shift with the risk of disturbing the functionality of the controlling circuitry or even triggering a latch-up. The substrate potential shift due to minority carrier injection by the lateral parasitic NPN transistor has been measured on a test chip and analyzed by 3D device simulation. The previously calibrated 3D device simulation and the measurements are in good agreement. The influence of protecting measures (substrate contacts) and the backside contact has been investigated experimentally. For the first time, the potential shift due to the parasitic substrate NPN transistor has been measured and simulated in 3D on an entire chip.

Boost PFC with 100-Hz switching frequency providing output voltage stabilization and compliance with EMC standards

Consumer and household applications require cheap AC/DC power supplies complying with EMC standards. Passive solutions are bulky and do not provide output voltage stabilization. Active solutions based on power-factor correctors (PFCs) with high-frequency switching provide compactness and regulation capability, but are generally expensive due to the need for fast-recovery diodes and complex EMI filters. This paper describes a boost PFC in which the switch is turned on and off only twice per line period. This results in limited di/dt and dv/dt and switch losses, allows use of slow-recovery diodes, and avoids the need for heavy EMI filters. In addition, the output voltage can be stabilized in a broad load range by a simple control. The switching unit, including control and protection, can also be integrated in a simple smart-power IC for large-volume applications.

A new lateral power MOSFET for smart power ICs: the “LUDMOS concept”

In this paper, a new concept of lateral DMOSFET for medium voltage (<100 V) smart power integrated circuits is proposed. These structures present a trench in the drift region filled with oxide or with oxide and polysilicon. These structures called LUDMOSFET feature a reduced specific on-resistance and enhanced breakdown voltage. For example, for a breakdown voltage of 50 V, the specific on-resistance is 1.2 mΩ cm 2 in the conventional LDMOSFET, 0.8 mΩ cm 2 in the LUDMOS without polysilicon (i.e. 30 percent reduction) and 0.6 mΩ cm 2 in the LUDMOS with polysilicon (i.e. 50 percent reduction). They are technologically compatible with advanced CMOS processes using trench isolation.

Reliability of smart power devices

Smart power devices of the last generation are able to integrate a full electronic system, including logic and analog functions and power drivers, in a true single chip solution exploiting the advanced features made available by mixed BCD processes developed for this purpose. The complexity of the ICs and their applications together with the severe stress conditions which these devices can experience in the field makes the reliability assurance of the Smart Power ICs a very challenging task and for this purpose a complete approach is necessary combining an application oriented IC qualification methodology with structural evaluations to test the intrinsic reliability of the basic process elements. In this context the knowledge of the main failure mechanisms is fundamental both for an effective detection in qualification and for an early prevention during IC design.