Modeling Lateral Parasitic Transistors in Smart Power ICs

Abstract

Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic transistors have to be included into a postlayout simulation. A methodology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behavior and accuracy of the model has been found