Abstract
A new method to efficiently describe parasitic bipolar structures in junction-isolated smart-power ICs is reported. Both two- and three-dimensional situations are tackled. An automatic simulation code for calculating the parasitic currents injected into the substrate by power devices, which may endanger the functioning of the signal-processing circuits, has been developed. Also, a Java graphical interface has been implemented with the aim of automatically managing the mixed circuit-device simulation. Examples of applications are given with reference to BCD5 technology.
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