SiON Interfacial Layer Research Articles

Deep insights into the mechanism of nitrogen on the endurance enhancement in ferroelectric field effect transistors: Trap behavior during memory window degradation

The nitridation process can significantly improve the quality of the interfacial layer and suppress the unrecoverable electron trapping of the interfacial states during cycling, which is the main cause of endurance enhancement. In this work, through in-depth analysis of defect behavior during memory window (MW) degradation in ferroelectric field effect transistors (FeFETs), it is found that the degradation of FeFET devices with SiON interfacial layer starts within the HZO layer, while the degradation process of FeFET devices with SiO2 interlayer initially begins at the interlayer and then penetrates into the HZO layer. First, the MW degradation processes of nitridation/non-nitridation devices are measured and compared. Moreover, through the extended measure-stress-measure method, three types of defects are defined and the defect behaviors including trapping kinetics and energy locations during degradation are systematically investigated. The mechanism of nitrogen on the endurance enhancement is finally revealed. These results are valuable to better understand the reliability issues of FeFET and pave the way for future process optimization.

Perhydropolysilazane derived SiON interfacial layer for Cu/epoxy molding compound composite

The interface of Cu/epoxy molding compound composite (Cu/EMC) faces threats from water and ionic compounds, which can induce the delamination of the Cu/EMC, and thus, affect the reliability of the most widely used composite in the semiconductor industry. Herein, we proposed a thin SiON interfacial layer converted from an inorganic polymer of perhydropolysilazane (PHPS), which not only improved the bonding strength of the Cu/EMC by up to 57% but also increased the durability of Cu/EMC in water and saturated NaCl solution. This thin interfacial layer has a negligible influence on the thermal conductive behavior of Cu/EMC, which is a vital parameter in microelectronic encapsulation. The interfacial bonding mechanism has been investigated, which verified a covalent bonding between Cu and SiON, as well as a synergistic effect of hydrogen bonding and mechanical interlocking between the EMC and SiON. This work thus presents a promising strategy to construct thin SiON interfacial layers to improve the bonding strength and increase the durability for Cu/EMC composites.

Optical band gap analysis and modeling for ultra-thin high-k dielectrics in high-k/metal gate transistors

A highly precise band gap measurement based on deep UV spectroscopic ellipsometry along with Bruggeman effective model approximation was developed for high-k/metal gate CMOS with ultrathin EOT (<1.5 nm). By applying and comparing the measurement for HfO2 on SiO2 and SiON interfacial layers with different thicknesses, N%, and annealing conditions, two new sub band gap states corresponding to nitrogen in the film are observed. Together with X-ray photoelectron spectroscopy and electrical measurements, it is found that the band gap energies can be correlated to N% and the leakage current of the high-k films by linear regression (R2 = 0.95). This indicates that the method is capable of quantifying physical and electrical properties of high-k dielectrics, and therefore a time consuming physical analysis or expensive electrical test on fully built devices for gate dielectrics can be avoided.

ALD Hf0.2Zr0.8O2and HfO2with cyclic annealing/SPA plasma treatment: reliability

The reliability of atomic layer-deposited Hf0.2Zr0.8O2and HfO2on a SiON interfacial layer (IL) with cyclic deposition and annealing (DADA) and cyclic deposition and slot-plane-antenna Ar plasma exposure (DSDS) is studied. The results are compared with control, that is, As-Deposited samples, without any treatment during or after the dielectric deposition. DSDS Hf0.2Zr0.8O2demonstrates a promising equivalent oxide thickness (EOT) downscaling ability, a reduced gate leakage current, and low mid-gap interface state density as compared to the control device, while DADA Hf0.2Zr0.8O2has degraded the value of EOT as well as a degraded interface. When devices are subjected to a constant voltage stress in the gate injection mode, DSDS Hf0.2Zr0.8O2showed a four times reduction in the flat-band voltage shift and a three order of magnitude reduction in the stress-induced leakage current within 100-s stress as compared to the control sample. The observed time to failure, T63%, is the highest for DSDS Hf0.2Zr0.8O2. The addition of Zr and the cyclic plasma exposure (DSDS process) seems to supress the oxide trap formation in Hf0.2Zr0.8O2films. When DSDS Hf0.2Zr0.8O2deposited on two different ILs, SiON and plasma oxynitride are compared, in that SiON demonstrates improved reliability as compared to plasma oxynitride.

Reliability of ALD Hf1-XZrxO2 Deposited by Intermediate Annealing or Intermediate Plasma Treatment

The reliability of atomic layer deposited Hf1-xZrxO2 with x=0.8 on a SiON interfacial layer (IL) has been analyzed in detail for three different oxide deposition processes, (i) DADA: samples were subjected to dielectric deposition and thermal annealing in a cyclical process; (ii) DSDS: samples were subjected to similar cyclical process with dielectric deposition and exposure to Ar plasma; and (iii) As-Dep: the dielectric for the control samples was deposited without any intermediate step. Capacitance-voltage and current-voltage characteristics of the MOS capacitors (MOSCAP) with metal gate (TiN), subjected to a constant field stress of 2.75 × 107 V/cm in the gate injection mode, show that the flat-band voltage shift (∆VFB ) and stress induced leakage current (SILC) below 100 s stress is the lowest for DSDS samples whereas the worst degradation was observed for DADA samples. However, identical degradation was observed in all sample types when stress was increased to 1000 s. Intermediate plasma exposure (DSDS process) seems to supress the oxide trap formation as it provides EOT downscaling ability and good reliability performance. The reliability characteristics, when compared with pure HfO2, seem to improve with the addition of ZrO2.

Impact of bilayer character on High K gate stack dielectrics breakdown obtained by conductive atomic force microscopy

The time to breakdown distribution of bilayer gate stack dielectrics is measured at nanometric scale using an atomic force microscope in conduction mode under ultra-high vacuum. The bilayer consists of a SiON interfacial layer and a HfSiON High-K layer. Thanks to the small tip/sample contact area the time to breakdown distribution of the single interfacial layer is measured separately. It is found that the Weibull parameters of the Interfacial layer distribution are the same as those of the high percentile part of the bilayer bimodal distribution. This experimentally confirms the validity of former dielectric breakdown model assumptions. Considering the fields in each layer an accurate evaluation of acceleration factors and voltage scaling of the bimodal distribution are given.

MOS Devices With High-κ (ZrO$_2$) $_x$(La $_2$O$_3$) $_{1-x}$ Alloy as Gate Dielectric Formed by Depositing ZrO $_2$/La$_2$O $_3$/ZrO$_2$ Laminate and Annealing

An amorphous (ZrO2)x(La2O3)1-x alloy formed by depositing a ZrO2/La2O3/ZrO2 laminate and a subsequent annealing was employed as the gate dielectric for metal-oxide-semiconductor (MOS) devices. The (ZrO2)x(La2O3)1-x alloy is found to have a high permittivity κ of 26.2 with negligible amount of bulk traps, both of which are very desirable for advanced gate dielectrics. By integrating the (ZrO2)x(La 2O3)1-x alloy with an SiON interfacial layer as the gate stack, it displays good frequency dispersion in capacitance-voltage (C -V) characteristics and low interfacial trap density of 1.52 × 1011 cm-2 eV-1. In addition, the current conduction mechanism of the gate stack is observed to be Fowler-Nordheim tunneling and the leakage current of 3.6 × 10-6 A/cm2 at the gate voltage of -1 V for equivalent oxide thickness of 1.1 nm can be achieved, which is superior to other high-κ dielectrics. Furthermore, satisfactory reliability is verified by bias temperature instability measurement. Most importantly, this gate stack not only exhibits a promising perspective for advanced CMOS technology but introduces a more reliable process to form an alloy-based high-κ gate dielectric.

Remote Plasma Enhanced Chemical Deposition of Non-Crystalline GeO<SUB>2</SUB> on Ge and Si Substrates

Non-crystalline GeO2 films remote were plasma deposited at 300 degrees C onto Ge substrates after a final rinse in NH4OH. The reactant precursors gas were: (i) down-stream injected 2% GeH4 in He as the Ge precursor, and (ii) up-stream, plasma excited O2-He mixtures as the O precursor. Films annealed at 400 degrees C displayed no evidence for loss of O resulting in Ge sub-oxide formation, and for a 5-6 eV mid-gap absorption associated with formation of GeOx suboxide bonding, x < 2. These films were stable in normal laboratory ambients with no evidence for reaction with atmospheric water. Films deposited on Ge and annealed at 600 degrees C and 700 degrees C display spectra indicative of loss of O-atoms, accompanied with a 5.5 eV absorption. X-ray absorption spectroscopy and many-electron theory are combined to describe symmetries and degeneracies for O-vacancy bonding defects. These include comparisons with remote plasma-deposited non-crystalline SiO2 on Si substrates with SiON interfacial layers. Three different properties of remote plasma GeO2 films are addressed comparisons between (i) conduction band and band edge states of GeO2 and SiO2, and (ii) electronic structure of O-atom vacancy defects in GeO2 and SiO2, and differences between (iii) annealing of GeO2 films on Ge substrates, and Si substrates passivated with SiON interfacial transition regions important for device applications.

Evaluation of the N- and La-induced defects in the high-κ gate stack using low frequency noise characterization

Low frequency noise (LFN) characterization was performed on the HfSiON gate stacks fabricated with the SiON interfacial layers (ILs) and a La cap layer. The LFN data identified N and La related defects located in the IL/HK region.

(ZrO2)x(La2O3)1-x Alloy as High-k Gate Dielectric for Advanced CMOS Devices

An amorphous (ZrO2)x(La2O3)1-x alloy formed by deposition of ZrO2/La2O3/ZrO2 laminate and a subsequent annealing was employed as the gate dielectric for MOS devices and the impact of a SiON interfacial layer on device performance was also explored in this work. The (ZrO2)x(La2O3)1-x alloy is found to have a high k value of 26.9 and tiny amount of bulk traps, both of which are very desirable for advanced high-k gate dielectrics. In addition, it is observed that the thermally grown SiON interfacial layer can prevent the formation of a silicide (ZrSi) and/or lower-k silicate (ZrSiO4) film during the subsequent annealing, which would cause poor interfacial qualities. By integrating the (ZrO2)x(La2O3)1-x alloy and SiON interfacial layer, MOS devices demonstrate a leakage current of 3×10-9 A/cm2 at gate voltage (Vg) of -1 V with EOT of 2.31 nm and this performance is superior to other high-k gate dielectrics.

Extended Scalability of HfON/SiON Gate Stack Down to 0.57 nm Equivalent Oxide Thickness with High Carrier Mobility by Post-Deposition Annealing

We discuss scaling the equivalent oxide thickness (EOT) of Hf-based high-k gate dielectrics by post-deposition annealing (PDA). Thin HfON/SiON gate stacks with EOT=0.57 nm were successfully formed by repeating ultra thin (0.6 nm) HfO2 deposition and high-temperature (950 °C) PDA on a previously formed SiON interfacial layer. Physical and electrical analyses revealed that the reduction in EOT was due to crystallization of HfON to the tetragonal phase which has a higher dielectric constant than the amorphous and other crystalline phases. It was also found that Hf diffusion in the SiON interfacial layer was induced by the high-temperature PDA treatment. This also improved the k-value of the interfacial layer and enabled aggressive scaling even when using a SiO2-based interfacial layer. The electron mobility of the gate stack is higher than those in the previous reports, indicating that a high quality interface is realized using this approach. The reduction in EOT together with the excellent interfacial quality demonstrated in the present study shows that this technique is a promising solution for the 22-nm-node and beyond.

Suppression of Ge–O and Ge–N bonding at Ge–HfO 2 and Ge–TiO 2 interfaces by deposition onto plasma-nitrided passivated Ge substrates

A study of changes in nano-scale morphology of thin films of nano-crystalline transition metal (TM) elemental oxides, HfO 2 and TiO 2, on plasma-nitrided Ge(100) substrates, and Si(100) substrates with ultra-thin (∼ 0.8 nm) plasma-nitrided Si suboxide, SiO x , x < 2, or SiON interfacial layers is presented. Near edge X-ray absorption spectroscopy (NEXAS) has been used to determine nano-scale morphology of these films by Jahn–Teller distortion removal of band-edge d-state degeneracies. These results identify a new and novel application for NEXAS based on the resonant character of the respective O K 1 and N K 1 edge absorptions. Their X-ray energy difference of > 150 eV is critical for this approach.

Suppression of Ge–O and Ge–N bonding at Ge–HfO 2 and Ge–TiO 2 interfaces by deposition onto plasma-nitrided passivated Ge substrates: Integration issues Ge gate stacks into advanced devices

A study of changes in nano-scale morphology of thin films of nano-crystalline transition metal (TM) elemental oxides, HfO 2 and TiO 2, on plasma-nitrided Ge(1 0 0) substrates, and Si(1 0 0) substrates with ultra-thin (∼0.8 nm) plasma-nitrided Si suboxide, SiO x , x < 2, or SiON interfacial layers is presented. Near edge X-ray absorption spectroscopy (NEXAS) has been used to determine nano-scale morphology of these films by Jahn-Teller distortion removal of band edge d-state degeneracies. These results identify a new and novel application for NEXAS based on the resonant character of the respective O K 1 and N K 1 edge absorptions. This paper also includes a brief discussion of the integration issues for the introduction of this Ge breakthrough into advanced semiconductor circuits and systems. This includes a comparison of nano-crystalline and non-crystalline dielectrics, as well as issues relative to metal gates.

Density functional study of initial HfCl 4 adsorption and decomposition reactions on silicon surfaces with SiON interfacial layer

The initial adsorption and decomposition of HfCl 4 on silicon surfaces with different types of SiON interfacial layers are investigated using density functional theory. We find that the reactions of HfCl 4 on both the hydroxylated and nitrided silicon surfaces proceed through similar reaction pathways. By comparison of the reaction energies of HfCl 4 with the hydroxyl and amino surface sites, we find that it is both kinetically and thermodynamically favorable for the reactions of HfCl 4 on hydroxyl site of silicon substrates. Comparing with the adjacent bridging oxygen, we also find that the neighboring hydroxyl can facilitate the adsorption of HfCl 4 on the amido surface site. Also, it is more kinetically and thermodynamically favorable for the reaction of HfCl 4 with bridging NH site than that with NH 2 site.

Nitrogen profile engineering in the interfacial SiON in a HfAlO/SiON gate dielectric by NO Re-oxidation

The effects of the nitrogen profile in the SiON-interfacial layer (IL) on the mobility in FETs employing a HfAlO/SiON gate dielectric have been investigated. In order to suppress the interdiffusion between HfAlO and SiON, the nitrogen concentration in SiON should be higher than 15 at%, while the substrate interface should be oxygen-rich in order to suppress the mobility reduction. By using an NO reoxidation of NH/sub 3/ formed 0.4-nm-thick silicon nitride, the mobility reduction due to the SiON-IL was successfully suppressed, and electron and hole mobility of 92% and 88% of those for SiO/sub 2/ at V/sub g/=1.1 V were obtained for HfAlO/SiON with equivalent oxide thickness (EOT) of 1.1 nm. By using nitrogen profile engineered SiON-IL, good equvalent oxide thickness (EOT) uniformity, low EOT, low gate leakage current, low defect density, and symmetrical threshold voltage were all achieved, indicating that a poly-Si/HfAlO/SiON gate stack would be a candidate as an alternative gate structure for low standby power FETs of half-pitch (hp)65 and hp45 technology nodes.

Electron mobility dependence on annealing temperature of W∕HfO2 gate stacks: The role of the interfacial layer

Interfacial layers between the high-k dielectric and Si surface have a very important role to play in the achievement of high electron mobilities required in the next generations of high performance silicon technologies. W∕HfO2 gate stacks formed on SiO2∕SiON interfacial layers subjected to various process conditions were characterized by electrical measurements such as electron mobility, inversion layer thickness, and leakage reduction with respect to standard SiO2 technology. The required high electron mobilities were obtained only when the W∕HfO2 gate stack was annealed at high temperature. Electrical data and physical analysis of the stack suggest intermixing of the HfO2 with the interfacial layer and formation of a silicate layer which may lessen the effects of phonon scattering. Densification of the interfacial layer by spike annealing or interfacial layer stabilization by nitrogen plasma inhibits such reactions and lower electron mobilities were obtained. Also, no electrical performance advantages are seen by thinning the HfO2 down to 1.5nm.

The Suppression of the Interfacial Reaction between HfAlOx/Interfacial Layers during Post Deposition Annealing

The reaction behavior of the Interfacial Layer (IL) in an HfAlOx/SiO2 and SiON structure during a post deposition annealing (PDA) in an N2-diluted oxygen ambient was examined. After a PDA at 1,050oC for 1 s, the 0.7 nm-thick IL was reduced if the O2 concentration was lower than 0.02%. The reduction of the IL led to the formation of defects and the Si migration to the HfAlOx surface, resulting in an increase in the C-V hysteresis. The amount of Si migrated to HfAlOx surface decreases with increasing the O2 concentrations during PDA and changing the interfacial layer from SiO2 to SiON. Even if SiON is used for interfacial layer, the decreasing of mobility was caused by nitrogen which stay in interface between SiON and substrate. Optimization of nitrogen in SiON interfacial layer is necessary. Electron and hole mobility of 75/77% of that for SiO2 were obtained for HfAlOx/SiON with EOT = 1.6 nm because of optimization of PDA O2 concentration and nitrogen profile in SiON.

Thermal Instability of Poly-Si Gate Al2O3 MOSFETs

The thermal stability of a SiO2/Al2O3 dielectric stack under high-temperature annealing after poly-Si gate deposition was examined. An interface reaction occurs when the activation temperature is higher than the post deposition annealing temperature, which results in the reduction of the interfacial oxide layer and hence silicate formation. As a result, the characteristics of metal oxide semiconductor field effect transistors (MOSFETs), such as mobility, reliability, and the distribution of capacitance are severely degraded. The formation of a SiON interfacial layer is found to be effective in suppressing the interface reaction.