MOS Devices With High-κ (ZrO$_2$) $_x$(La $_2$O$_3$) $_{1-x}$ Alloy as Gate Dielectric Formed by Depositing ZrO $_2$/La$_2$O $_3$/ZrO$_2$ Laminate and Annealing

Abstract

An amorphous (ZrO2)x(La2O3)1-x alloy formed by depositing a ZrO2/La2O3/ZrO2 laminate and a subsequent annealing was employed as the gate dielectric for metal-oxide-semiconductor (MOS) devices. The (ZrO2)x(La2O3)1-x alloy is found to have a high permittivity κ of 26.2 with negligible amount of bulk traps, both of which are very desirable for advanced gate dielectrics. By integrating the (ZrO2)x(La 2O3)1-x alloy with an SiON interfacial layer as the gate stack, it displays good frequency dispersion in capacitance-voltage (C -V) characteristics and low interfacial trap density of 1.52 × 1011 cm-2 eV-1. In addition, the current conduction mechanism of the gate stack is observed to be Fowler-Nordheim tunneling and the leakage current of 3.6 × 10-6 A/cm2 at the gate voltage of -1 V for equivalent oxide thickness of 1.1 nm can be achieved, which is superior to other high-κ dielectrics. Furthermore, satisfactory reliability is verified by bias temperature instability measurement. Most importantly, this gate stack not only exhibits a promising perspective for advanced CMOS technology but introduces a more reliable process to form an alloy-based high-κ gate dielectric.