Single Processor Architecture Research Articles

Algorithms to Speed up Contour Tracing in Real Time Image Processing Systems

Contour tracing is an important pre-processing step in many image processing applications such as feature recognition, biomedical imaging, security and surveillance. As single processor architectures reach their performance limits, parallel processing architectures offer energy efficient and high performance solutions for real time applications. Parallel processing architectures, are thus used for several real time image processing applications. Among the several interconnection schemes available, Cayley graph based interconnections offer easy routing and symmetric implementation capabilities. For parallel processing systems with a Cayley graph based interconnection scheme, torus, we developed three accelerated algorithms corresponding to three existing families of contour tracing algorithms. We simulated these algorithms on a parallel processing framework to quantify the normalized speed-up possible in any torus connected parallel processing system. We also compared our best performing algorithm with the existing parallel processing implementations for Nvidia GPUs. We observed a speed-up of up to 468 times using our algorithms on a parallel processing architecture in comparison to the corresponding algorithm on a single processor architecture. We evaluated a speed up of 194 (and 47) compared to the existing parallel processing contour tracing implementation on Tesla K40c (and Quadro RTX 5000 GPU hardware respectively). We observe that for torus connected parallel processing architectures used for image processing, our algorithms can be used to speed up contour tracing, without any hardware modification.

A Radiative Transfer Module for Relativistic Magnetohydrodynamics in the PLUTO Code

Abstract We present a numerical implementation for the solution of the relativistic radiation hydrodynamics and magnetohydrodynamics equations, designed as an independent module within the freely available code PLUTO. The radiation transfer equations are solved under the gray approximation and imposing the M1 closure, which allows the radiation transport to be handled in both the free-streaming and diffusion limits. Equations are integrated following an implicit–explicit scheme, where radiation–matter interaction terms are integrated implicitly, whereas transport and all of the remaining source terms are solved explicitly by means of the same Godunov-type solvers included in PLUTO. Among these, we introduce a new Harten–Lax–van Leer–contact (HLLC) solver for optically thin radiation transport. The code is suitable for multidimensional computations in Cartesian, spherical, and cylindrical coordinates using either a single processor or parallel architectures. Adaptive grid computations are also made possible by means of the CHOMBO library. The algorithm performance is demonstrated through a series of numerical benchmarks by investigating various different configurations with a particular emphasis on the behavior of the solutions in the free-streaming and diffusion limits.

Experiences of Civil Certification of Multi-Core Processing Systems in Commercial and Military Avionics, Integration Activities, and Analysis

<div class="section abstract"><div class="htmlview paragraph">Avionics systems are currently undergoing a transition from single core processor architectures to multi-core processor architectures. This transition enables significant advantages in reduction in size, weight, power (SWaP) and cost. However, avionics hardware and software certification policies and guidance are evolving as research and experience is gained with multi-core processor architectures. The unique challenges of using multi-core processors in certified avionics will be discussed. The requirements for a virtualization platform supporting multiple real-time operating system (RTOS) partitions on a multi-core processor used in safety-critical avionics systems are defined, including the ability to support multiple design assurance levels (DAL) on multiple cores, fault isolation and containment, static configuration as per ARINC 653, role-based development as per DO-297, and robust partitioning to reduce cost of incremental certification. The paper will present a collaborative approach undertaken by a leading avionics system supplier and a leading safety-critical commercial-off-the-shelf (COTS) RTOS supplier in the development of a multi-core real-time system with DO-178C DAL A software and DO-254 DAL A hardware safety certification on an FAA Program of Record (PoR). The approach taken to comply with FAA CAST-32A objectives will be presented. Particular focus is provided for integration activities and program specific analysis performed by the IMA application developer and integrator to guarantee determinism in the deployed system. Using the approach defined under the PoR, the application developer performs activities including foot-printing under worst-case execution time (WCET) loads and application of numerical methods to predict interference effects. The IMA integrator uses this data to define a performance restricted environment (PRE) and uses WCET verification in the PRE. Tools, analysis methods, and sample results will be presented. The method to capture results is discussed. Finally the paper includes lessons learned during the program.</div></div>

Simulation of Flying Parallel Modelling in Computer

The existence of types of mathematical models is conditioned by characteristics of the examined object. The process of synchronizing program modules employs this division in Information and Communication Technologies that are examined and optimized for the simulation process. The main problem in the process of synchronization is that how computing is done by the distributed control system – cluster or network. How can conditions of mathematical models be managed and how computing can become a creative and effective process. The physics of simulation model is well done and it is examined by their parameters easily. Now this model construction for some time is able to simulate the design of models very authentically. This work focuses on this very important field of science and technical community. The theory of design of decentralized computer control systems are derived from computers that create a distributed computer system of a flight simulator. Modelling of a time benefit of a simulator system is done by description using equations depending on architecture of computer systems. An important part of this article is the way of analysis types of mathematical models, a simulation method and an analytical approach, a corresponding calculation of a control implemented in single-processor architecture.

TH Express-2 reaches new heights for supercomputer interconnects

Modern supercomputers are highly dependent on parallel processing to boost their performance, and thus are all effectively parallel computers. The basic architecture of a parallel computer is composed of two parts: a single processor architecture and a communication architecture [1]. The latter is mainly implemented and supported by the interconnection network. During the design of an interconnection network, the following aspects must be considered carefully: (i) The communication requirements of the system, and the type of communication abstract that will be delivered to the programmer. (ii) The performance requirements of the network, in terms of both pointto-point communication and collective communication performances, ensure that the overall system is balanced with respect to communication speed and computation speed. (iii) The type of interconnection topology required to reduce the average distance between nodes (and thus reduce communication latency) while maintaining a moderate number of links (enabling increased communication bandwidth without making the implementation overly complex). (iv) The type of communication protocol to be used, including the routing algorithm (how to deliver messages from one node to another) and the flow control mechanism (how to handle congestion when it occurs in network traffic). (v) Implementation of the network with appropriate building blocks, including host interfaces, switches, routers, and electrical or optical cables.

Graceful Overload Management in Firm Real-Time Systems

Real-time embedded systems have to provide the highest Quality of Service despite possible processing overloads. In such systems, programs are characterized by upper bounds on finishing times and the QoS is assessed by the ratio of successful deadlines. In this article, we deal with this issue. We focus on single processor architectures in the framework of firm real-time applications that accept deadline missing under some specified limits. Tasks are assumed to be periodic. We present a novel model for tasks which is called BGW model. It is drawn from two approaches respectively known as the skip-over model and the Deadline Mechanism. We propose specific dynamic priority schedulers based on EDF (Earliest Deadline First) for BGW task sets and we briefly report the results of a simulation study.

ARCHITECTURE AND IMPLEMENTATION ISSUES OF MULTI-CORE PROCESSORS AND CACHING – A SURVEY

As the performance gap between processors and main memory continues to widen, increasingly aggressive implementations of cache memories are needed to bridge the gap. This paper includes what brought about the change from single processor architecture to having multiple processors on a single die and some of the hurdles involved, and the technologies behind it. Having each processor on a single die allows much greater communication speeds between the processors. For multi-threading and multitasking, security and virtualization and physical restraints such as heat generation and die size, we need multi-core processor. Processor cache is the performance bottleneck in most current architectures. Next, we consider some of the issues involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the increasingly stringent design targets and constraints of multi-processors.

Power Efficiency for Hardware/Software Partitioning with Time and Area Constraints on MPSoC

Hardware/software partitioning is a crucial step in hardware/software co-design for energy-efficient, high-performance systems. Previous research efforts mainly focused on single processor architecture. Their methods can not produce high-quality solutions to the problem of hardware/software partitioning for multiprocessor systems. In this paper, we propose two algorithms for hardware/software partitioning problem on MPSoC, to minimize power consumption with time and area constraints. The Tree_Partitioning algorithm generates optimal partitioning results for tree-structured control-flow graphs using dynamic programming. For the general partitioning problem, we propose the DAG_Partitioning algorithm to produce near optimal solution efficiently for directed-acyclic graphs. The experimental results show that our proposed algorithms outperform existing techniques for a set of benchmarks with various time and area constraints.

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has moved on the number of cores. Consequently, the fundamental feature of system designs and their associated design flows and tools need to change, so that, to support the scalable parallelism and the design portability. The same feature can be exploited to design reconfigurable hardware, such as FPGAs, which leads to rethink the mapping of sequential algorithms to HDL. The sequential programming paradigm, widely used for programming single processor systems, does not naturally provide explicit or implicit forms of scalable parallelism. Conversely, dataflow programming is an approach that naturally provides parallelism and the potential to unify SW and HDL designs on heterogeneous platforms. This study describes a dataflow-based design methodology aiming at a unified co-design and co-synthesis of heterogeneous systems. Experimental results on the implementation of a JPEG codec and a MPEG 4 SP decoder on heterogeneous platforms demonstrate the flexibility and capabilities of this design approach.

Power and performance analysis of multimedia applications running on low-power devices by cache modeling

High processing speed is required to support computation intensive applications. Cache memory is used to improve processing speed by reducing the speed gap between the fast processing core and slow main memory. However, the problem of adopting cache into computing systems is twofold: cache is power hungry (that challenges energy constraints) and cache introduces execution time unpredictability (that challenges supporting real-time multimedia applications). Recently published articles suggest that using cache locking improves predictability. However, increased cache activities due to aggressive cache locking make the system consume more energy and become less efficient. In this paper, we investigate the impact of cache parameters and cache locking on power consumption and performance for real-time multimedia applications running on low-power devices. In this work, we consider Intel Pentium-like single-processor and Xeon-like multicore architectures, both with two-level cache memory hierarchy, using three popular multimedia applications: MPEG-4 (the global video coding standard), H.264/AVC (the network friendly video coding standard), and recently introduced H.265/HEVC (for improved video quality and data compression ratio). Experimental results show that cache locking mechanism added to an optimized cache memory structure is very promising to increase the performance/power ratio of low-power systems running multimedia applications. According to the simulation results, performance can be improved by decreasing cache miss rate down to 36 % and the total power consumption can be saved up to 33 %. It is also observed that H.265/HEVC has significant performance advantage over H.264/AVC (and MPEG-4) for smaller caches.

Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems

Conventional digital signal processor (DSP) based digital controllers are not specifically optimized for multi-rail DC-DC converter applications. A new application-specific instruction-set processor (ASIP) that overcomes the shortcomings of existing controllers has thus been designed, implemented, and evaluated. The proposed dual multiply-accumulate (MAC) architecture has been implemented using a field programmable gate array and verified in a closed-loop power converter system. The benefits of the proposed ASIP are illustrated through a comparison with a conventional single MAC processor architecture. Experimental results demonstrate improved output voltage transient response compared with existing DSP-based controllers when controlling multiple DC-DC converters. In the case of multiple converters that have a non-integer switching frequency ratio more significant improvements in transient response are obtained due to the processor's interrupt controller.

A Parallel Encryption Algorithm Based on Piecewise Linear Chaotic Map

We introduce a parallel chaos-based encryption algorithm for taking advantage of multicore processors. The chaotic cryptosystem is generated by the piecewise linear chaotic map (PWLCM). The parallel algorithm is designed with a master/slave communication model with the Message Passing Interface (MPI). The algorithm is suitable not only for multicore processors but also for the single-processor architecture. The experimental results show that the chaos-based cryptosystem possesses good statistical properties. The parallel algorithm provides much better performance than the serial ones and would be useful to apply in encryption/decryption file with large size or multimedia.

Implementation of FFT on General-Purpose Architectures for FPGA

This paper describes two general-purpose architectures targeted to Field Programmable Gate Array (FPGA) implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip (MP-SoC). Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors’ approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA.

Learning and backtracking in non-preemptive scheduling of tasks under timing constraints

We propose two novel heuristic search techniques to address the problem of scheduling tasks under hard timing constraints on a single processor architecture. The underlying problem is NP-hard in the strong sense and it is a fundamental challenge in feedback-control theory and automated cybernetics. The proposed techniques are a learning-based approaches and they take much less memory space. A partial feasible schedule is maintained and extended over a repeated problem solving trials, previously assigned priorities are refined according to the gained information about the problem to lead the convergence to a complete feasible schedule if one exists. First, we present the learning in hard-real-time with single learning (LHRTS-SL) algorithm where a single learning function is utilized, then we discuss its drawback and we propose the LHRTS with double learning algorithm in which a second learning function is integrated to cope up with LHRTS-SL drawback. Experimental results show the efficiency of the proposed techniques in terms of success ratio when used to schedule randomly generated problem instances.

Parallel, stochastic measurement of molecular surface area

Biochemists often wish to compute surface areas of proteins. A variety of algorithms have been developed for this task, but they are designed for traditional single-processor architectures. The current trend in computer hardware is towards increasingly parallel architectures for which these algorithms are not well suited. We describe a parallel, stochastic algorithm for molecular surface area computation that maps well to the emerging multi-core architectures. Our algorithm is also progressive, providing a rough estimate of surface area immediately and refining this estimate as time goes on. Furthermore, the algorithm generates points on the molecular surface which can be used for point-based rendering. We demonstrate a GPU implementation of our algorithm and show that it compares favorably with several existing molecular surface computation programs, giving fast estimates of the molecular surface area with good accuracy.

Lock-free dynamic hash tables with open addressing

We present an efficient lock-free algorithm for parallel accessible hash tables with open addressing, which promises more robust performance and reliability than conventional lock-based implementations. "Lock-free" means that it is guaranteed that always at least one process completes its operation within a bounded number of steps. For a single processor architecture our solution is as efficient as sequential hash tables. On a multiprocessor architecture this is also the case when all processors have comparable speeds. The algorithm allows processors that have widely different speeds or come to a halt. It can easily be implemented using C-like languages and requires on average only constant time for insertion, deletion or accessing of elements. The algorithm allows the hash tables to grow and shrink when needed. Lock-free algorithms are hard to design correctly, even when apparently straightforward. Ensuring the correctness of the design at the earliest possible stage is a major challenge in any responsible system development. In view of the complexity of the algorithm, we turned to the interactive theorem prover PVS for mechanical support. We employ standard deductive verification techniques to prove around 200 invariance properties of our algorithm, and describe how this is achieved with the theorem prover PVS. CR Subject Classification (1991): D.1 Programming techniques AMS Subject Classification (1991): 68Q22 Distributed algorithms, 68P20 Information storage and retrieval

Discrete simulation of large aggregates of neurons

Realistic simulation of aggregates of neurons often utilises compartmental models which limit the scope of the simulations with single processor architectures to small or medium size networks (typically hundreds of neurons). An alternative approach, based on cell automata models, allows efficient simulation of nervous tissue by modelling neurons as finite state automata. In this paper, data structures and algorithms appropriate for efficient simulation of message-based event-driven models of neurons in single processor architectures are presented. With these techniques, the simulation of large networks (of the order of 10 5 neurons with 10 2 synapses per neuron) becomes feasible.

Operation-saving VLSI architectures for 3D geometrical transformations

Two VLSI architectures for the computationally efficient implementation of the elementary 3D geometrical transformations are introduced. The first one is based on a single floating-point multiply/add unit, while the other one comprises a four processing-element vector unit. By exploiting the structure of the elementary transformation matrices, some of the elements of which are ones and zeros, the proposed architectures avoid full-matrix multiplication for the matrix multiplications involved in the calculation of the transformation matrix by treating them as updates of specific elements, the new values of which are obtained by scalar operations in the case of the single-processor architecture or by simple vector operations in the case of the processor array. Thus, the floating-point operation count and the number of memory accesses required by a transformation are reduced and, therefore, the performance of the circuit which computes the transformation matrix, in terms of execution time, is improved at minimal hardware cost. Furthermore, a circuit is proposed which, for each sequence of transformations, selects the most appropriate direction for computing the product of the matrices in the corresponding stack of transformation matrices in order to further reduce the number of floating-point operations compared to the case where the direction of the computation of the successive matrix products is predetermined. The proposed single-processor architecture is suitable for low-cost applications, while the parallel execution scheme implemented by the introduced parallel processor may be implemented by any four-PE processor with small overhead.

Monitoring and control system based on microcomputer for synchronous generator

Normally in a electrical power plant, the parameters involved on the generation process are monitored through electromechanical instruments and controlled by analog regulators. A new alternative is proposed in this work. It presents a digital control and monitoring system for a turbine and synchronous generator. A single processor architecture IBM-PC and a multifunction data acquisition board with its signal conditioning circuits are used. Four sensors based on microcomputers are performed: load angle for synchronous machine; phase angle; power factor; and electric frequency.

An autonomous I/O module for low-cost media on-demand servers

This paper focuses on the design of low cost media-on-demand servers. Limitations of single-processor architectures and their input/output subsystems are shown. An original device called autonomous media I/O module (AMIOM) is proposed. The device consists of a local CPU, a local buffer memory, and an interconnection unit that allows the communication with two subordinate buses. The objective is to migrate the stream and its control from the host and to make the I/O subsystem scalable. Features of the proposed AMIOM are presented in detail. The interconnection and operation of multiple modules are discussed. Performance of the improved design is evaluated with taking into consideration communication overheads. The effect of attaching multiple I/O devices to each of the module's subordinate buses is also analyzed. Comparison of the classical design and the improved one shows significant performance gain.