Abstract
Hardware/software partitioning is a crucial step in hardware/software co-design for energy-efficient, high-performance systems. Previous research efforts mainly focused on single processor architecture. Their methods can not produce high-quality solutions to the problem of hardware/software partitioning for multiprocessor systems. In this paper, we propose two algorithms for hardware/software partitioning problem on MPSoC, to minimize power consumption with time and area constraints. The Tree_Partitioning algorithm generates optimal partitioning results for tree-structured control-flow graphs using dynamic programming. For the general partitioning problem, we propose the DAG_Partitioning algorithm to produce near optimal solution efficiently for directed-acyclic graphs. The experimental results show that our proposed algorithms outperform existing techniques for a set of benchmarks with various time and area constraints.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
