Single Event Upset Research Articles

Pulsed-Laser-Induced Single-Event Upset in Dynamic Comparator by Incorporating Experimental Parameters Into Simulations

Pulsed-Laser-Induced Single-Event Upset in Dynamic Comparator by Incorporating Experimental Parameters Into Simulations

Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

With the development of nanoscale circuit technology, the on-track error rate of digital circuit and the effect of single event upset have become more pronounced. The radiation resistance research on DICE SRAM or DICE flip-flop device has been carried out extensively, including 65 nm, 90 nm, and 130 nm. However, the research on 55 nm DICE latch has not been reported. Using a three-dimensional device model of the 55 nm bulk silicon process established by the simulation tool TCAD, we verify the reinforcement performance of the DICE circuit, and clarify the effects of different incident conditions on DICE circuits. At the same time, we carry out a comparison of anti-SEU performance between NMOS transistor and PMOS transistor in the 55 nm process through comparative simulation experiments and quantitative analysis. The result shows that one of the important factors is the LET value which affects the generation rate of electron-hole pairs. A higher LET value will extend the upset recovery time of device and increase the peak of voltage. In addition, the difference in charge-sharing mechanism between transistors leads to the recovery time of PMOS higher than that of NMOS. As the angle of incidence increases, the charge-sharing mechanism between adjacent devices is enhanced, and electron-hole pairs ionized in sensitive regions increase. Due to the difference in charge mobility, the sensitivity of the angle of incidence of Nhit in DICE is much greater than that of Phit. Therefore, strict tilt angle incident test evaluation is required for DICE device before practical application. Finally, the large distance between adjacent MOS tubes will weaken the charge-sharing mechanism and reduce the charge collection of adjacent MOS tubes. Simulation result shows that the distance between the MOS transistors in the 55 nm process cannot be less than 1.2 μm. The relevant simulation results can provide a theoretical basis and data for supporting the study of the physical mechanism of SEU and reinforcement technology, thereby promoting the application of memory devices to the aerospace field.

Quantification of neutron-induced single event upsets in a static random-access memory by clinical high-energy photon beam

Quantification of neutron-induced single event upsets in a static random-access memory by clinical high-energy photon beam

Measurement of Neutron-induced Single Event Upset Cross-Section of UltraScale Kintex FPGA Using Time-of-Flight Technique

Measurement of Neutron-induced Single Event Upset Cross-Section of UltraScale Kintex FPGA Using Time-of-Flight Technique

Characteristics of secondary ions and their impact on single-event upset in TMD devices under proton irradiation

Transition metal dichalcogenide (TMD) materials are emerging candidates for next-generation electronics due to their unique properties, such as high carrier mobility and on/off ratios. However, their introduction may significantly alter single-event effects (SEEs) in devices compared to traditional silicon devices. This work investigates the SEE sensitivity of TMD devices under proton irradiation using the Geant4 simulation toolkit. Secondary ions generated by proton irradiation of TMD devices with different proton energies were simulated and analyzed. The energy deposition in the device's sensitive volume array was also examined. The results show that TMD devices are more susceptible to SEEs than silicon devices, and that their SEE sensitivity depends on the TMD material, proton energy, and critical charge. These findings provide valuable insights into the aerospace application of TMD material devices and the design of radiation-hardened TMD-based electronics.

Evaluation of Single Event Upset on a Relay Protection Device

Traditionally, studies have primarily focused on single event effects in aerospace electronics. However, current research has confirmed that atmospheric neutrons can also induce single event effects in China’s advanced technology relay protection devices. Spallation neutron irradiation tests on a Loongson 2K1000 system-on-chip based relay protection device have revealed soft errors, including abnormal sampling, refusal of operation and interlock in the relay protection device. Given the absence of standardized evaluation methods for single event effects on relay protection devices, the following research emphasizes the use of Monte Carlo simulation and software fault injection. Various types of single event upsets, such as single bit upsets, dual bit upsets, and even eight bit upsets, were observed in Monte Carlo simulations where atmospheric neutrons hit the chip from different directions (top and bottom). The simulation results indicated that the single event effect sensitivity of the relay protection device was similar whether the neutron hit from the top or the bottom. Through software fault injection, the study also identified soft errors caused by neutron induced single event upsets on the Loongson 2K1000 system, including failure to execute, system halt, time out, and error result. And the soft error number of system halts and error results exceeded that of time outs and failures to execute in all three tested programs. This research represents a preliminary assessment of single event effects on relay protection devices and is expected to provide valuable insights for evaluating the reliability of advanced technology relay protection devices.

Study of Single-Event Effects Influenced by Displacement Damage Effects under Proton Irradiation in Static Random-Access Memory

Static random-access memory (SRAM), a pivotal component in integrated circuits, finds extensive applications and remains a focal point in the global research on single-event effects (SEEs). Prolonged exposure to irradiation, particularly the displacement damage effect (DD) induced by high-energy protons, poses a substantial threat to the performance of electronic devices. Additionally, the impact of proton displacement damage effects on the performance of a six-transistor SRAM with an asymmetric structure is not well understood. In this paper, we conducted an analysis of the impact and regularities of DD on the upset cross-sections of SRAM and simulated the single-event upset (SEU) characteristics of SRAM using the Monte Carlo method. The research findings reveal an overall increasing trend in upset cross-sections with the augmentation of proton energy. Notably, the effect of proton irradiation on the SEU cross-section is related to the storage state of SRAM. Due to the asymmetry in the distribution of sensitive regions during the storage of “0” and “1”, the impact of DD in the two initial states is not uniform. These findings can be used to identify the causes of SEU in memory devices.

Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset.

This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally, SEUs are considered to have negative effects on electronic systems or designs, but the current study demonstrates that they can also have positive contributions to the DNN on the MPSoC. The assertion that SEUs can have positive contributions to electronic system design was supported by conducting fault injections through dynamic reconfiguration on DNNs implemented on a 16nm FinFET technology Zynq UltraScale+ MPSoC. The results of the current study were highly significant, indicating that an SEU in configuration memory could result in an impressive 8.72% enhancement in DNN recognition on the MPSoC. One possible cause is that SEU in the configuration memory leads to slight changes in weight or bias values, resulting in improved activation levels of neurons and enhanced final recognition accuracy. This discovery offers a flexible and effective solution for boosting DNN performance on the MPSoC platform.

Design of soft error correction flip-flop cells for highly reliable applications

With the development of technology, the vulnerability of integrated circuits to Single Event Effect (SEE) increases, and the sensitivity of flip-flops to soft errors induced by Single Event Transient (SET) and Single Event Upset (SEU) increases. Fault tolerant design is necessary for high reliability applications. In this work, a Soft Error Correction Flip-Flop 1(SEC FF1) is proposed, which can correct soft errors induced by SET and SEU at low clock phase without additional clock cycle. It has the lowest area and power consumption overhead and the lowest Power-Delay Product (PDP) compared with other radiation hardened flip-flops. In order to correct soft errors earlier, a variant of SEC FF1, SECFF2, is proposed at the cost of power consumption and switching delay. As the feature size of transistors shrinks, Double Node Upset (DNU) induced by single-event charge sharing is becoming an emerging reliability challenge. In order tolerate DNU, variant of SEC FFs, DNU Correction (DNUC) FFs, are proposed. In addition, the delay element used in the radiation-hardened flip-flops is also introduced.

Geomagnetic Storm Effects on the LEO Proton Flux During Solar Energetic Particle Events

AbstractDuring a few solar energetic particle (SEP) events, solar protons were trapped within the geomagnetic field and reached the outer edge of the inner radiation belt. We reproduced this phenomenon by modeling the proton flux distribution at the Low‐Earth Orbit (LEO) for different geomagnetic conditions during solar particle events. We developed a three‐dimensional relativistic test particle simulation code to compute the 70–180 MeV solar proton Lorentz trajectories in low L‐shell range from 1 to 3. The Tsyganenko model (T01) generated the background static magnetic field with the IGRF (v12) model. We have selected three Dst index values: −7, −150, and −210 nT, to define quiet time, strong, and severe geomagnetic storms and to generate the corresponding inner magnetic field configurations. Our results showed that the simulated solar proton flux was more enhanced in the high‐latitude regions and more expanded toward the lower latitude range as long as the geomagnetic storm was intensified. Satellite observations and geomagnetic cutoff rigidities confirmed the numerical results. Furthermore, the LEO proton flux distribution was deformed, so the structure of the proton flux inside the South Atlantic Anomaly (SAA) became longitudinally extended as the Dst index decreased. Moreover, we have assessed the corresponding radiation environment of the LEO mission. We realized that, for a higher inclined LEO mission during an intense geomagnetic storm (Dst = −210 nT), the probability of the occurrence of the Single Event Upset (SEU) rates increased by 19% and the estimated accumulated absorbed radiation doses increased by 17% in comparison with quiet conditions.

Total ionizing dose and single event effect response of 22 nm ultra-thin body and buried oxide fully depleted silicon-on-insulator technology

The test chip including transistors and Static Random Access Memory (SRAM) is proposed and fabricated by an advanced 22 nm Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-on-Insulator (UTBB FD-SOI) technology. Experimental results of Co-60 irradiation and heavy ion experiments are presented. Total Ionizing Dose (TID) experiment results show that the threshold voltage shift of the transistor is about 100 mV when the dose is 500 krad(Si) and the SRAM irradiated to a dose of at least 300 krad(Si) can maintain its functionality, which means that 22 nm UTBB FD-SOI devices exhibit significantly improved total dose tolerance performance compared to the previous generation process. TID-induced threshold voltage shift in conventional-well nMOSFET can be mitigated by applying biasing to back-gate, while back-gate biasing is invalid for TID mitigation of the conventional-well pMOSFET. Heavy ion experimental results make known that 22 nm UTBB FD-SOI technology has contributions to Single Event Effect (SEE) hardness and the hardened SRAM has higher single event upset (SEU) tolerance and even SEU immunity. The research indicates that the circuits manufactured by 22 nm UTBB FD-SOI technology have great potential space applications in harsh radiation environments.

Exploring the impact of shrinking feature sizes on proton-induced saturation SEU cross-section through simulation

In the study reported here, Monte Carlo simulations were used to investigate single-event upsets (SEUs) induced by ultra-high-energy proton irradiation in electronic devices made with various technology nodes, and the simulation results show the following. For smaller technology nodes, the SEU cross section tends to increase when the incident proton energy exceeds 200 MeV, and the dependence of the SEU cross section on 200-MeV protons as a saturation point for technology nodes smaller than 90 nm might result in underestimated error rates. Finally, using proton SEE cross section data with energies higher than 200 MeV can better assess the severity of the non-saturation effect, and can also obtain more realistic error rate.

A Total Self Checking Comparator Implementable on FPGAS Using Bist Technology

an integrated circuits (IC) "manufacturing tests" may be made easier to administer with the use of design for testability (DFT). Integrated circuits' embedded memory tests make use of the TSC (TSC) approach. We have shown the TSC method and several algorithms used in TSC for the purpose of testing embedded memory in this article. An address generator, controller, comparator, and memory are the four main components of this kind of memory TSC technology. This paper details the three memory TSC controller implementation techniques. The memory TSC controller is modelled in Verilog HDL, and its accuracy is checked using the RTL compiler before synthesis.
 Here we provide a way to build TSC comparators for TSC systems that may be implemented on FPGAs—totally self-checking (TSC) systems—that can be used online. By directly measuring the output of each lookup table (LUT), this approach may be utilised to do comprehensive online diagnostics of all LUTs. This entails mapping the basic components of the comparator with a limited number of test patterns. With our technique, we can achieve exhaustive diagnosis with a small number of test patterns on the order of n [O(n)] (where n is the input number to the comparator) while yet covering all bases 100% of the time, even if we are just aware of the LUT's specs and not its exact structure. For systems that need absolute reliability, FPGAs will be a perfect fit. Our experiment also included a single-event upset (SEU) induced by neutron radiation to validate the soft error rate (SER) in a field-programmable gate array (FPGA) based on static random-access memory (SRAM).

SEU protection design for the prototype readout electronics of MAPS-based STCF inner tracker

The Super Tau Charm Facility (STCF) is a high-luminosity electron-positron collider experiment operating at center-of-mass energy of 2–7 GeV. Its primary goal is to explore flavor physics, CP-violations, and investigate physics beyond the Standard Model. The inner tracker (ITK) is a crucial component of the STCF tracking system, which is responsible for detecting particle hits, especially those with low momentum below 100 MeV/c. Its primary objectives include providing high detection efficiency and spatial resolution for charged particle tracks. However, the electronics of ITK is susceptible to single-event upset (SEU) caused by beam-related background. To address this, this paper presents a prototype of FPGA (Field Programmable Gate Array)-based electronics that can detect and automatically repair SEU induced soft errors in its Configuration Random Access Memory (CRAM) and whose Block Random Access Memory (BRAM) has been also subjected to commonly used hardening techniques. Importantly, the prototype's corrective operations do not result in any dead time due to hot redundancy backup. In the laboratory environment, we measured the bit error rate of the data transmission to be lower than 10-12 with a confidence level of 99.99%. Through neutron beam experiments conducted at China Spallation Neutron Source (CSNS) back-n white neutron source. We demonstrated that the readout electronics can effectively restore correct functionality and promptly rectify soft errors.

High radiation tolerant SOT-MRAM read peripheral circuit with fast data recovery

With downscaling of process technology, single event upsets (SEUs) induced by radiation particles are becoming an important threat to the reliability of memories. Particularly, the charge sharing effect is more significant, causing multiple node upsets due to a single event. Spintronic memory is a viable contender for addressing this challenge, since magnetic tunnel junction (MTJ), the core component of spintronic memory, has been shown to be intrinsically immune to radiation effects. However, hybrid spintronic/CMOS peripheral circuits are still vulnerable to radiation effects. This paper proposes a novel radiation-hardened read circuit with recovery time and radiation tolerance optimized for spin–orbit torque magnetic random access memory (SOT-MRAM). The obtained results show that the proposed circuit can be highly resilient to SEUs independent of its polarity. It can tolerate 8.06X, 10.41X, 9.8X, and 3.49X more critical charge as compared to the 13T, 11T, 11T, and CMOS cross-coupled transistor radiation hardened circuits, respectively with some area overhead. Moreover, the proposed circuit has the least recovery time compared to the previously reported radiation hardened MRAM cell.

Characterization of Single Event Effect in a Radiation Hardened Programmable Read-Only Memory in a 130 nm Bulk CMOS Technology

The concept of memory that can only be read but cannot be changed seems strange at first. In reality, it is found that it has great application potential, such as the processor with a fixed purpose, the initial set value of the microprocessor BIOS, and these data are stored in Programmable Read-Only Memory (PROM) to quickly realize system functions. The PROM storage content is fixed, greatly simplifying his design. The radiation of space particles is the main factor causing the failure of the electronic system of spacecraft. The PROM storage array of the space electronic system is the most basic guarantee for the normal operation of the electronic system. The chip adopts domestic 130 nm standard technology of Complementary Metal Oxide Semiconductor (CMOS), Muller-C digital filter is used in the peripheral subsystem of PROM storage array, and the core cell uses Dual Interlocked Cell (DICE) and ring gate and other radiation hardening technologies to design a 32Kx8bit radiation resistant asynchronous programmable PROM. Pre-silicon of devices was verified by Technology Computer Aided Design (TCAD), and post silicon radiation verification was completed through radiation experiment. The post silicon radiation experiment showed that the total ionizing Dose (TID) capacity of the PROM chip was ≥100 Krad (Si), the critical value of single event upset (SEU) was ≥37.1 MeV·cm2/mg, the critical value of single event latch up was ≥98 MeV·cm2/mg, meeting the life requirements of the initial value storage of aerospace electronic systems. These performances ensure the reliable operation of the space electronic system after restart.

Influence of 0.1–10 MeV neutron-induced SEUs on estimation of terrestrial SER in a nano-scale SRAM

The impact of 0.1–10 MeV neutron-induced single-event upsets (NSEUs) on terrestrial SER (soft error rate) prediction is analyzed for several broad spectrum neutron sources based on 0.1–200 MeV NSEU energetic-dependent cross-sectional data of a 40 nm SRAM. The results show that for test facilities with abundant <10 MeV neutrons, such as ISIS ChipIR, J-PARC BL10, CSNS Back-n, and CSNS BL09, the terrestrial SER is overestimated. The overestimation could reach 78%–287%. By reducing the cutoff energy (Emin) from 10 to 6 MeV, the overestimation can be decreased. However, the overestimation can still reach up to 164% in this case, significantly larger than the results reported by previous studies. By analyzing the contribution of neutrons in different energy bins to NSEUs, the discrepancy is proved to be attributed to the sensitivity of NSEUs to 0.1–1 MeV neutrons, along with the overpopulation of 0.1–1 MeV neutrons for certain test facilities, such as ISIS ChipIR and CSNS BL09. Therefore, it is necessary to take 0.1–1 MeV NSEU sensitivity into account when studying the prediction method using broad spectrum neutron sources.

Design optimization of a Dual-Interlocked-Cell in 65 nm CMOS tolerant to Single Event Upsets

Dual-Interlocked-Cell (DICE) latches are tolerant to Single Event Effects (SEE) by design owing to intrinsic redundancy. In nanometric technologies, as in the 65 nm scale, there are new SEE vulnerabilities associated with charge sharing between nodes. Herein we present a systematic analysis of the robustness against radiation using a simulation software tool for analog and mixed-signal circuits (AFTU) that emulates the possible effects generated by particle impacts. In this paper, we evaluate the influence of SEE on circuit performance using this tool as an RHbD assessment for designers. An exhaustive study of the possible vulnerabilities of the DICE architecture is performed, including an evaluation of the proximity between critical nodes at the layout level. As a result, we propose several modifications to the cell implementation to optimize its robustness against Single Event Upsets (SEU). An assortment of five designs with different variations of the original DICE scheme was sent for fabrication on a new chip and tested under ion beams, with promising results showing a clear improvement in the SEU sensitivity of the cell. The best results come from a redesign of the load circuitry to avoid a SET2SEU effect and full interleaved layout to avoid charge sharing effects after a single event.

Impact of aging on the SEU immunity of FinFET-based embedded memory systems

Due to the rapid technology evolution, embedded computing systems have become a pervasive part of daily life, used for tasks ranging from cost-driven edge computing in the Internet of Things (IoT), up to high-end critical applications (such as aerospace and defense). However, no matter which electronic system the memories are embedded in, they tend to occupy up to 90 % of the total area of the silicon wafer. On the other hand, accelerated aging (bias-temperature instability: BTI) due to technology scaling has become a major factor in degrading memory immunity to transient faults (single-event upsets: SEUs). In this scenario, memory reliability concerns have been brought to the forefront. In the light of the above mentioned, this paper analyses the impact of aging on the SEU immunity of 14 nm FinFET SRAM cell-based embedded memory systems. Experimental results based on HSpice simulations have shown that under certain operating conditions, for 10-year life span, the 6 T SRAM cell SEU immunity can degrade by 58.9 % with respect to the fresh cell (not aged). Moreover, cell aging is strongly dependent on parameters like the temperature in which the cell is operating, as well as the frequency by which the content stored in the cell is inverted during its lifetime. A 256MByte memory system was designed. Simulations indicate that the Mean Time Between Failures (MTBF) of this memory system can degrade up to 23.4 % after a period of 10 years.

Fault Detection and Analysis in SRAM through Self Refreshing Operation

Numerous soft faults in SRAM memory emerge as technological innovations scales down, resulting in single and several cell upsets. The increased use of transistors in space applications has rendered semiconductor devices more vulnerable to soft errors caused by harm from radiation. A single event upset (SEU) is occurring whenever a soft error produces a tiny bit flipped in a storage device. Because SEU faults affect system performance, they must be addressed as soon as possible. Error-correcting codes, like the method known as (7,4) hamming codes, were devised and their decoding and encoding procedures were verified. It also used to detect single errors that can be fixed. It also helps detect double errors, SECDED however repair of double errors is tough. The decoding and encoding techniques of these approaches were investigated, and all computational findings had been verified and executed in a Xilinx NEXYS 4 DDR FPGA board.