High radiation tolerant SOT-MRAM read peripheral circuit with fast data recovery

Abstract

With downscaling of process technology, single event upsets (SEUs) induced by radiation particles are becoming an important threat to the reliability of memories. Particularly, the charge sharing effect is more significant, causing multiple node upsets due to a single event. Spintronic memory is a viable contender for addressing this challenge, since magnetic tunnel junction (MTJ), the core component of spintronic memory, has been shown to be intrinsically immune to radiation effects. However, hybrid spintronic/CMOS peripheral circuits are still vulnerable to radiation effects. This paper proposes a novel radiation-hardened read circuit with recovery time and radiation tolerance optimized for spin–orbit torque magnetic random access memory (SOT-MRAM). The obtained results show that the proposed circuit can be highly resilient to SEUs independent of its polarity. It can tolerate 8.06X, 10.41X, 9.8X, and 3.49X more critical charge as compared to the 13T, 11T, 11T, and CMOS cross-coupled transistor radiation hardened circuits, respectively with some area overhead. Moreover, the proposed circuit has the least recovery time compared to the previously reported radiation hardened MRAM cell.