Abstract
This brief proposes a new design technique for spin-orbit torque magnetic random access memory (SOT-MRAM), suitable for high-density and low-power on-chip cache applications. A bitline of the proposed memory bit cell is shared with that of an adjacent bit cell leading to a reduction in the number of metals along the column direction. This results in higher integration density due to improved metal pitch limited region. The proposed memory can optimize the bit-cell area by aggressively reducing the size of write access transistor, since SOT-based switching operation of SOT devices translates to smaller size of write access transistor. Furthermore, the proposed SOT-MRAM still retains the advantages of SOT-MRAM such as low write energy dissipation, high read-disturb margin, and improved reliability of magnetic tunnel junction. In comparison with the conventional SOT-MRAM bit cells, our proposed MRAM bit cell can have 20% less bit-cell area. Even compared with the standard STT-MRAM, our proposed bit cell still achieves higher integration density. Moreover, the shared bitline SOT-MRAM achieves >6× lower write power and higher read-disturb margin than does the STT-MRAM.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.