Single Event Burnout Research Articles

Energy Dependence of Atmospheric Neutron-Induced Failures in Silicon Carbide Power Devices

A time-of-flight measurement technique is used to determine energy-dependent neutron cross sections of silicon carbide power devices exposed to a beam that approximates atmospheric neutrons up to 600 MeV. The Irradiation of Chip Electronics (ICE)-II neutron beam at the Los Alamos Neutron Science Center (LANSCE) is used during these experiments. The measurements show that a wide range of neutron energies are likely to cause device failures close to the rated voltage, from neutron interactions with lattice atoms within the active device volume. The data indicate that the energy-dependent cross sections are relatively large, revealing a high probability for a few percent of the neutron–lattice atom interactions to give rise to a failure when the device is biased close to its rated voltage. Additionally, knowledge of the neutron energies and associated cross sections giving rise to failures within these devices provide insights regarding the critical charges and the sensitive volumes of these devices as a function of neutron energy for single-event burnouts. Lastly, the energy-dependent cross sections provide a preliminary set of data to calculate a correlation factor between failure rates obtained using a broad energy neutron source, and the commonly used mono-energetic high-energy proton beams, utilized due to their wider availability for determining bias dependent failure-in-time curves.

Single Event Burnout Hardening Technique for High-Voltage p-i-n Diodes With Field Limiting Rings Termination Structure

High-voltage p-i-n diodes for space applications are sensitive to single event burnout (SEB), which may cause the failure of the entire electronic system. This article describes the SEB failure mechanism of high-voltage p-i-n diodes with field limiting rings (FLRs) termination structure, based on the electro-thermal coupled transient simulation model in the Sentaurus TCAD simulator. The simulation results show that the catastrophic failures result from the intense local heating at the edge of the main junction, because the high electric field strength at this region induces strong impact ionization of the charge carriers. The strike at the edge of the main junction shows the strongest sensitivity to SEB since the energetic particle-induced carriers are deposited exactly at the high electric field region. Then, a novel SEB hardening technique of localized carrier lifetime control at the edge of the main junction region is proposed based on the analysis on the failure mechanism. Our simulation results demonstrate that the reduction of the localized carrier lifetime can alleviate the peak electric field and reduce the local heat accumulation, thereby improving the SEB performance of high-voltage p-i-n diodes.

Impact of Heavy-Ion Irradiation in an 80-V Radiation-Hardened Split-Gate Trench Power UMOSFET

In this work, the single-event burnout (SEB) and degradation behaviors induced by heavy-ion irradiation were investigated in an 80-V-rated SEB-hardened split-gate trench (SGT) power U-shaped metal-oxide-semiconductor field-effect transistor (UMOSFET). After SEB hardening, the SEB failure threshold voltage of the sample device was measured to be 90 V; furthermore, a permanent degradation of the drain leakage or gate leakage was found after irradiation when the reverse voltage exceeded 60 V. The simulation results demonstrate that the heavy-ion-induced transient high temperature is a common mechanism responsible for the severe degradation and the catastrophic SEB. In addition, an effective method to improve the degradation and SEB tolerances, which enhances the rated breakdown voltage of a device, was proven through simulations.

Study of the single-event burnout triggering criteria and hardening of the 550 V SOI lateral-IGBT

In this paper, we study the single-event burnout (SEB) tolerance of the 550 V SOI Lateral-IGBT (SOI-LIGBT). The TCAD simulations are performed to inspect the SEB triggering criteria. The SEB of SOI-LIBGT is caused by the ionized carriers induced latch-up of the inherent parasitic thyristor. The peak value of base-emitter voltage (Vbe) in the parasitic NPN transistor is used as the critical parameter to inspect whether the SEB occurs. An analytical model is brought up to reveal the failure procedure during SEB and the hardening strategy. The hardening SOI-LIGBT with the shallow p + layer (SPL-LIGBT) is proposed to improve the SEB immunity by reducing peak Vbe. It is verified by both analytical model and TCAD simulations that the SEB threshold voltage (VSEB) can be enhanced to 250 V at the linear energy transfer (LET) of 37 MeV·cm2/g in the blocking state.

Simulation-based study of single-event burnout in 4H-SiC high-voltage vertical superjunction DMOSFET: Physical failure mechanism and robustness vs performance tradeoffs

We explore and elucidate physical failure mechanisms in a 4H-SiC, high voltage, superjunction (SJ) vertical DMOSFET from a single heavy ion strike using three-dimensional electro-thermal transient simulations. The single-event burnout (SEB) failure is thermal runaway from second breakdown, initiated by impact ionization and terminated with mesoplasma formation, at the center of the P-pillar/N+ substrate interface. We also demonstrate that the SEB performance of this SiC SJ DMOSFET is insensitive to the pillar width but sensitive to the strike location with ion strike at the P-pillar causing SEB at a lower blocking voltage than at the N-pillar. Compared to commercially available 1.2 kV blocking-rated non-SJ DMOSFETs, which have been demonstrated to survive SEB up to 525 V, the SJ DMOSFET increases SEB survival threshold voltage (VSEB) by a factor of 2.2, making it close to 1200 V, while the on-resistance is increased by only 11%. Using our recently developed figure of merit (FoM), which considers the trade-off between VSEB and on-state performance, we find that the SiC SJ DMOSFET achieves a FoM that is 14 times better, making it superior to conventional 1.2 kV SiC DMOSFETs for long-term radiation-tolerant operation in space applications.

Research of single event burnout in a high-performance radiation-hardened SOI lateral power MOSFET

In this paper, a 60 V radiation-hardened SOI lateral power MOSFET (LDMOS) device is proposed and single event burnout (SEB) failure mechanism of the device is investigated by Sentaurus simulator. The SOI LDMOS device, with 2 μm drift region and extended N+ drain region, can achieve optimal breakdown voltage (BVDS, 67 V) and specific on-resistance (Ron,sp, 5 mΩ·cm2), while Ron,sp of the device without extended N+ drain is 5.6 mΩ·cm2. Sensitive region of the device for SEB is analyzed and the most sensitive region for SEB is near the center of drift region. The influence of different linear energy transfers (LETs) on SEB threshold voltage is explored and the device can survive at the full drain to source voltage (VDS) biasing of 60 V even for a highly-energetic ion with LET of 1 pC/μm (96 MeV·cm2/mg). Besides, heavily-doped P+ region is inserted on the source side and parameters of source region are optimized to improve SEB tolerance of the device. Second breakdown voltage of the device which correlates with SEB failure threshold is up to 66 V, indicating excellent SEB hardness of the device. Eventually, SEB failure mechanism of the device is investigated in detail and the action of the parasitic npn bipolar junction transistor (BJT) inherent in the device structure is the key to SEB tolerance of the device.

Damage mechanism of SiC Schottky barrier diode irradiated by heavy ions

In this paper, the failure mode and mechanism of silicon carbide (SiC) Schottky barrier diode (SBD) irradiated by high-energy tantalum (Ta) ions are studied. The experimental results show that the reverse bias voltage during irradiation is the key factor causing the failure of SiC SBDs. When the reverse bias of the device is 400 V, the heavy ions will cause the single event burnout (SEB), and a “hole” formed by the melting of SiC material appears in the irradiated device. When the reverse bias is 250–300 V, the failure is manifested as the off state leakage current increases with the ion fluence. The higher the bias voltage of the device, the higher the leakage increase rate caused by heavy ions. For the devices with increased leakage, the leakage channels caused by heavy ions are found in the whole active region, based on microscopic analysis. The TCAD simulation results show that the incidence of heavy ions will lead the lattice temperature to increase in the device, and the maximum lattice temperature increases with bias voltage increasing. When the bias voltage is large enough, the local lattice temperature inside the device reaches the melting point of SiC material, resulting in SEB. When the bias voltage is relatively low, the lattice temperature is lower than the melting point of SiC material, so it will not cause burnout. However, the maximum lattice temperature in the device is concentrated near the Schottky junction, and the melting point of Schottky metal is much lower than that of SiC material. This may lead the Schottky junction to damage locally and eventually produce leakage path.

A 15 V-Tolerant and Radiation-Hardened MOSFET Driver With Positive and Negative References

Radiation-hardened and high-voltage power circuits are key components in aerospace applications. However, when working at high voltages, the effects of the total ionizing dose (TID) and the single event limit the application of power driving circuits in a radiation environment. A 15 V-tolerant radiation-hardened MOSFET driver was designed. The circuit architecture, which is based on positive and negative references, can reduce the gate source voltage of the transistors to less than 5&#x00A0;V, allowing the selection of thin-gate oxide high-voltage transistors. On this basis, adopting enclosed layout transistor (ELT) N-channel metal oxide semiconductor (NMOS) transistors helps the driver to obtain a good resilience to TID hardness. Additionally, this work optimized the layout of high-voltage N-type laterally diffused metal oxide semiconductor (LDMOS) transistors in the driver to effectively improve the single-event burnout (SEB) threshold. Three chips with different N-type drift region lengths were designed and fabricated in a 0.35&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> BCD process. The test results showed that the TID hardening capability of these chips with ZENER references and ELT NMOS transistors all exceeded 100 krad (Si). In addition, this driver was tested under heavy ion irradiation with linear energy transfer (LET) exceeding 75 MeV&#x00B7;<inline-formula><tex-math notation="LaTeX">$\dot\mathrm{{c}}{\mathrm{{m}}^{2}}\mathrm{{/mg}}$</tex-math></inline-formula>. The results show that this driver with a 6.6&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> drift region length had no single event latchup (SEL), single event gate rupture (SEGR), or single event burnout (SEB) sensitivity.

Simulation Study of Single-Event Burnout for the 4H-SiC VDMOSFET with N+ Split Source

Silicon Carbide (SiC) power MOSFET is the next generation device in the supply system of spacecraft. However, the current degradation or catastrophic failure of the power device could be induced when a drain voltage exceeds critical condition. In this article, an improved VDMOSFET structure for the Single-Event Burnout (SEB) is demonstrated. The improved power VDMOSFET includes a P+ shielding region at the JFET region. Meanwhile, forming a CSL layer by ion-implantation at the JFET to reduce the specific on-resistance. The device is etched in both sides to form trench and then implanting N-type impurities at the side walls of the trench to form the N+ split source (SDS-VDMOSFET). The 2-D numerical simulator Silvaco Atlas was used to study the SEB performance for the 1.2 kV-rated SiC SDS-VDMOSFET in a high linear energy transfer (LET) value of 0.5 pC/μm. The simulation results show that the improved structure can effectively reduce the peak lattice temperature induced by heavy-ion and increase the SEB threshold voltage compared with the standard VDMOSFET. Furthermore, the improved structure also presents a lower specific on-resistance. As a result, the maximum temperature of the standard VDMOSFET has exceeded 3000 K at a drain voltage of 400 V. However, the maximum temperature of the improved VDMOSFET is only 2090 K at a drain voltage of 800 V.

Research on Single Event Burnout of GaN power devices with femtosecond pulsed laser

The femtosecond pulsed laser is used to study the quantitative evaluation technology of the single event burnout (SEB) effect in GaN power devices. In this work, we establish two pulsed-laser effective energy transmission models for different device structures, analyzing and verifying the equivalent relationship between the effective laser energy and the heavy ion linear energy transmission (LET). The critical parameters of models are confirmed, including laser parameters and device parameters. The interface reflectivity between the layers is mainly considered. Meanwhile, the parameters are corrected by the multiple reflections between the interfaces, and the laser energy of the second reflection of the metal layer is considered. These measures can be used to reduce the error of the effective energy in the device active area. In addition, we validate the models experimentally. A gallium nitride high electron mobility transistor (GaN HEMT) and a schottky barrier diode (SBD) power device are used in the experiment on the irradiation by a femtosecond pulse laser. The effective laser energy thresholds and the laser equivalent LET threshold with two incident wavelengths of the SEB are calculated. The theoretical calculation value and the actual measured value are compared. The selcction basis of the laser wavelengths is given by the detailed study. The support for the laser quantitative evaluation and the protection design of the SEB in GaN power devices is provided by this work.

A Comparative Study of Single-Event-Burnout for 4H-SiC UMOSFET

SiC UMOSFET is a kind of significant power device in the supply of aerospace. But it is sensitive to space radiation. In this paper, the discrepancy of SEB behavior and research of 4H-SiC UMOSFET with the different values of particle linear energy transfer (LET) are proposed and investigated by the 2D numerical simulations. And the improved MOSFET with multi-Buff was compared with the conventional UMOSFET. At last, simulation results demonstrated that under high-intensity radiation environment (high LET value heavy ion incidence), the proposed UMOSFET could increase the single-event burnout (SEB) hardness, and using the lattice temperature of device as the SEB behavior characterization of the SiC UMOSFET after heavy ion incidence is more reasonable and accurate than only using high steady-state drain current.

A possible single event burnout hardening technique for SiC Schottky barrier diodes

SiC Schottky barrier diodes (SBDs) are sensitive to single event burnout (SEB) caused by the high-energy particle strikes, which greatly restricts their applications in the aerospace field. In this paper, we investigate the SEB performance of SiC SBDs with the electro-thermal coupled simulation model using the Sentaurus TCAD simulator. The simulation results show that reducing the reverse voltage can improve the SEB robustness because of the lower impact ionization rate and current density at lower reverse voltage. Based on this, we propose a novel SEB hardening technique of connecting two SiC SBDs in series. Since the voltage across the diode which is hit by the heavy ion can transfer to the other diode in time, the peak temperature attained is greatly reduced, and the SEB robustness is effectively improved for the hardening structure. Due to the low on-state resistance and power dissipation of SiC SBDs, the doubling of the on-state resistance for the series structure will not be a problem. In addition, with the advantages of simple implementation and strong recoverability, the hardening structure proposed in this paper is expected to be applied in practice. • A novel single event burnout hardening technique for SiC Schottky barrier diodes has been proposed. • The SEB robustness of SiC Schottky barrier diodes is effectively improved for the hardening structure. • The hardening structure has no special processing requirements and is easy to implement.

SiC double-trench MOSFETs with source-recessed structure for enhanced ruggedness

A novel SiC double-trench MOSFET (DT-MOS) with source-recessed structure is proposed and investigated via Sentaurus TCAD simulations in this paper. The lateral resistance area beneath the source region is completely eliminated, thus suppressing the turn-on of the parasitic npn transistor effectively. As a result, the short-circuit withstanding time, the single pulse avalanche energy (E av) under unclamped inductive switching test and the threshold voltage for single-event burnout are improved by 28%, 14% and 67%, respectively, when compared to the traditional state-of-the-art SiC DT-MOS, indicating its great potential for harsh environment applications.

Heavy-ion induced single event effects and latent damages in SiC power MOSFETs

The advantages of silicon carbide (SiC) power MOSFETs make this technology attractive for space, avionics and high-energy accelerator applications. However, the current commercial technologies are still susceptible to Single Event Effects (SEEs) and latent damages induced by the radiation environment. Two types of latent damage were experimentally observed in commercial SiC power MOSFETs exposed to heavy-ions. One is observed at bias voltages just below the degradation onset and it involves the gate oxide. The other damage type is observed at bias voltages below the Single Event Burnout (SEB) limit, and it is attributed to alterations of the SiC crystal-lattice. Focused ion beam (FIB) and scanning electron microscopy (SEM) were used to investigate the damage site. Finally, a summary of the different types of damage induced by the heavy ion in SiC MOSFETs is given as a function of the ion LET and operational bias.

(Invited) Total Dose Effects and Single Event Upsets During Radiation Damage of GaN and SiC

In critical defense applications and autonomous vehicles, there is an increasing transition from high-voltage Si power devices, which are limited in current ratings and power efficiency, to commercial wide bandgap (WBG) power devices. SiC and GaN power devices are now used in the automotive, wireless, and industrial power markets, but their adoption into space and avionic applications is hindered by their susceptibility to permanent degradation and catastrophic failure from heavy-ion exposure. Efforts to space qualify WBG power devices have revealed they are susceptible to damage from the high-energy, heavy-ion space radiation environment (galactic cosmic rays) that cannot be shielded. Higher voltage devices are more susceptible to these effects; as a result, to date, there are space-qualified GaN transistors now available, but limited to 300 V. Recent radiation testing of 600-V and higher GaN transistors has shown failure susceptibility at about 50% of the rated voltage, or less. Similarly, SiC power devices have undergone several generations of advances commercially, improving their overall reliability, but catastrophically fail at less than 50% of their rated voltage. SiC components have demonstrated susceptibility to radiation damage under heavy-ion single-event effects testing, reducing their utility in the space galactic cosmic ray (GCR) environment. In SiC-based Schottky diodes, catastrophic single-event burnout (SEB) and other single-event effects (SEE) have been observed at ~40% of the rated operating voltage, as well as an unacceptable degradation in leakage current at ~20% of the rated operating voltage. SEE caused by terrestrial cosmic radiation (neutrons) have also been identified by industry as a limiting factor for the use of SiC-based electronics in aircraft. Currently, small satellite applications require a Total Ionizing Dose (TID) resilience of 30 krad (Si) and Single Event Latch-up (SEL) hardened up to 80 MeV-cm2/mg linear energy transfer. Radiation hardening comes with a cost. As with Si power MOSFETs, electrical performance will suffer from hardening techniques. The two primary failure radiation damage concerns in current generations of electronics for space applications are (i) Single event upset, in which incident ionizing radiation results in the flipping of a bit from 0 to 1 or vice versa. While this may be a problem for data loss or operation, it does not lead to permanent damage of the device and (ii) Total dose failure, in which irradiation leads to the creation of a sufficient density of defects. These then lead to degradation of the electrical properties to the point of permanent failure. In this talk we will review radiation damage results for GaN and SiC and compare these to initial data for Ga2O3.Work performed as part of Interaction of Ionizing Radiation with Matter University Research Alliance (IIRM-URA ) , sponsored by the Department of the Defense, Defense Threat Reduction Agency under award HDTRA1-20-2-0002. The content of the information does not necessarily reflect the position or the policy of the federal government, and no official endorsement should be inferred. *Current address: Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, WI 53706

Simulation Study on Single-Event Burnout in Rated 1.2-kV 4H-SiC Super-Junction VDMOS

This article presents the 2-D numerical simulation results of the heavy-ion-induced leakage current degradation and single-event burnout (SEB) in the rated 1.2-kV silicon-carbide (SiC) super-junction (SJ) vertical diffusion metal-oxide-semiconductor (VDMOS). The employed simulation physics models were validated by the heavy-ion irradiation experiments of the commercially rated 1.2-kV SiC common VDMOS (C-VDMOS), which indicated a severe degeneration threshold of 500 V. The SiC common SJ VDMOS (C-SJ VDMOS) was proven to be sensitive to high-energy heavy-ion and represents comparative SEB performance compared with the SiC C-VDMOS. The robustness of the SiC SJ VDMOS with different single buffer layer (SBL) designs against a heavy-ion was simulated. It is found that the maximum temperature in the source metal/SiC interface and bottom of the structure could be compromised by the thickness of the buffer layer. As a result, the SiC SJ VDMOS with an optimal SBL exhibited a severe degeneration threshold of 800 V, which was a 60% increase compared to the SiC C-SJ VDMOS.

(Invited) Total Dose Effects and Single Event Upsets During Radiation Damage of GaN and SiC

SiC and GaN power devices are used in the automotive, wireless, and industrial power markets, but their adoption into space and avionic applications is hindered by their susceptibility to permanent degradation and catastrophic failure from heavy-ion exposure. Efforts to space-qualify wide bandgap power devices have revealed that they are susceptible to damage from the high-energy, heavy-ion space radiation environment (galactic cosmic rays) that cannot be shielded. GaN and SiC transistors have shown failure susceptibility at about 50% of the rated voltage. SiC components have demonstrated susceptibility to radiation damage under heavy-ion single-event effects testing, reducing their utility in the space galactic cosmic ray (GCR) environment. In SiC-based Schottky diodes, catastrophic single-event burnout (SEB) and other single-event effects (SEE) have been observed at ~40% of the rated operating voltage, as well as an unacceptable degradation in leakage current at ~20% of the rated operating voltage.

Investigation and improvement of single-event burn-out in 4H-SiC trench insulated gate bipolar transistors

In this paper, the triggering process for single-event burnout (SEB) in conventional 4H-SiC trench insulated gate bipolar transistors (C-TIGBTs) is described. Furthermore, SEB is studied for both a conventional structure and a new structure. The new structure has a Schottky contact at the collector side (S-TIGBT) and is investigated using a 2D numerical-simulation. The simulation results indicate that the Schottky-junction improves the SEB threshold voltage from 4000 V, in the C-TIGBT, to 4600 V, in the S-TIGBT, while the SEB-induced breakdown voltage for 75 MeV/(mg⋅cm−2) is improved by about 15.0%.

Single Event Burnout Hardening of Enhancement Mode HEMTs With Double Field Plates

Single event burnout (SEB) of enhancement mode GaN high-electron mobility transistors (HEMTs) under heavy ion irradiation is systematically studied based on simulations in this work. Susceptibility to SEB of different particle incidence environments is investigated to determine the device's sensitive position. Under these conditions, the mechanism of SEB in enhancement mode HEMTs is mainly associated with the charge congestion and subsequent continuous impact ionization. A hardened HEMT structure with the gate and drain double field plates is proposed correspondingly. Apart from better output characteristics and almost 25% improvement of breakdown voltage, the hardened structure also demonstrates better tolerance of SEB. This hardened structure can modify the electric field in the high field region so that charge accumulation is reduced significantly, thus effectively decreasing the possibility of SEB's occurrence. With a vertical heavy ion strike of 63.8 MeV ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg linear energy transfer (LET), SEB threshold voltage of the conventional structure HEMT is 160 V, while that of the hardened structure HEMT is much higher, reaching 249 V. Besides, the hardened device exhibits better SEB tolerance than the conventional device even at different higher LET conditions. Furthermore, the contribution to SEB tolerance of each field plate is also discussed.

Study on proton-induced single event effect of SiC diode and MOSFET

Proton-induced degradation and catastrophic failures in 650 V SiC diode and 900 V SiC MOSFET under different bias voltage and different proton energy are investigated. The experimental results show that when the bias voltage of SiC diode and MOSFET reaches 88% of rated voltage, 20 MeV protons will not cause the single event burnout (SEB) of two SiC devices. When SiC devices are burned out, a wave-shaped pulse current appears, the pulse current peak value gradually decreases, and the total pulse current width is within 5 microseconds. With the increase of bias voltage, the SEB fluence of SiC device is significantly reduced. After SiC diode is burned out, its reverse breakdown voltage is lower than 1 V, and the forward current when device has not been turned on is up to 8 orders of magnitude higher than before irradiation; the reverse breakdown voltage of SiC MOSFET is also lower than 1 V after burning out, only some SiC MOSFETs still maintain transfer characteristics under a voltage bias of 700 V, and the gate-source current has increased by 7–8 orders of magnitude compared to before irradiation. The Monte Carlo simulation results show that the linear energy transfer (LET) of 20 MeV proton in the epitaxial layer is lower than 2 MeV·cm2/mg, which is not enough to generate charge required for SEB. And the randomness of interaction between protons and device materials leads to different SEB fluences for SiC devices under different proton energies.