Abstract
A novel SiC double-trench MOSFET (DT-MOS) with source-recessed structure is proposed and investigated via Sentaurus TCAD simulations in this paper. The lateral resistance area beneath the source region is completely eliminated, thus suppressing the turn-on of the parasitic npn transistor effectively. As a result, the short-circuit withstanding time, the single pulse avalanche energy (E av) under unclamped inductive switching test and the threshold voltage for single-event burnout are improved by 28%, 14% and 67%, respectively, when compared to the traditional state-of-the-art SiC DT-MOS, indicating its great potential for harsh environment applications.
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