Single-ended Amplifier Research Articles

An advanced solid-state RF power source maximizing energy efficiency for optimal superconducting RF cavity charging

Abstract This paper outlines an experimental demonstration of an envelope tracking (ET) technique applied to a kilowatt-level single-ended solid-state power amplifier (SSPA), aimed at enhancing the charging efficiency of superconducting radio frequency (SRF) cavities by reducing reflection power while maintaining a high degree of efficiency. The technique is particularly designed for the pulsed operation of the European Spallation Source (ESS) at a nominal frequency of 352 MHz, with a 5% duty cycle and a pulse width of 3.5 ms. The study introduces an optimal charging scheme using a solid-state-based amplifier to maintain high efficiency, allowing for power ramp-up while minimizing reflections from SRF cavities and optimizing SSPA efficiency. A fast envelope tracking power supply (ETPS) system is implemented for the approximately 300 ms charging time required by the SRF cavities at ESS. The ETPS system, demonstrated on a single module as a proof-of-concept with scalability potential to a 400 kW power station, indicates an overall average efficiency of 70% and a 24% energy saving over traditional vacuum-tube based amplifiers. This demonstrates the ET technique’s effectiveness at the kilowatt level for efficient SRF cavity charging with reduced reflection, offering significant efficiency and energy savings.

Design of a Ka-band power amplifier

This paper introduces the design of a type of power amplifier working in the Ka-band, which has three stages based on 45nm CMOS technology. The operating frequency is 25-27GHz, and it has good efficiency and linearity. Among them, the driving stage adopts a cascode structure, the power stage adopts common source structure, and the matching network adopts a transformer structure. Using Cadence Virtuoso for simulation at the operating voltage of 1.8V, power gain of the single-ended power amplifier is 44.76 dB, saturation output power is 14.66 dBm, the output power at the 1dB compression point is 12.9dBm, and corresponding power-added efficiency is 22.19%.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques.

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

CMOS readout FEE based TV-BLR module for CdZnTe pixel detectors in high count rate applications

In this study, a time-variant baseline restorer (TV-BLR) circuit was designed and implemented to address the poor frequency selectivity issue in the shaping units of most state-of-the-art readout electronics for CdZnTe/CdTe detectors used in biomedical imaging applications. The proposed circuit improves image quality by canceling the artifacts that result from poor temporal and energy resolution in PET imaging. The proposed circuit consists of a Charge Sensitive Preamplifier (CSP) followed by a classical pole-zero compensation circuit. Two stages of integrators are added and a frequency rectifier module named the TV-BLR circuit has been built. The open-loop amplifier for the CSP is a single-ended input stage amplifier, designed for low-power applications with a maximum power consumption of 43 µW from a 1.2 V supply voltage, verified through post-layout Monte Carlo simulations. The TV-BLR increases the selectivity of the shaping filter, lowers the equivalent noise charge (ENC), and restores the baseline of the circuit to only 143 µV dc-offset. It also extends the counting rate behavior of the system by handling the time-over-threshold (ToT), which depends on the tail current (Itail) of the comparator stage. The circuit was designed, simulated, and validated for an input dynamic of 2–12.5fC, providing an energy range of 55.1–354.3 keV. The design has a charge-to-voltage conversion factor of 56.7 mV/fC with a 4% non-linearity error for an input detector capacitance of 200 fF, while achieving an optimal ENC of 57.4 e − RMS ± 0.1 e−/fC with 13.27 ns peaking time. Process Voltage Temperature (PVT) analysis was performed to validate the simulation results and performance metrics of the design. The proposed design improves energy resolution and avoids energy losses due to the readout system.

Single-ended amplifier-based touch readout circuit with immunity to display noise

To suppress errors in a touch readout circuit due to display noise, differential sensing using fully differential amplifiers is widely used. However, conventional differential sensing methods require additional circuits or increase circuit complexity, thus increasing power consumption and circuit area or requiring additional dummy RX line on the touch panel. In this study, we propose a compact touch readout circuit composed of a single-ended amplifier while keeping the display noise suppression of differential sensing so as to minimize power consumption and circuit area increase and avoid the need for additional dummy RX line. The proposed touch readout circuit for is fabricated in circuit area of 0.4 mm2 with 0.35 µm 3.3 V CMOS process and measured for 10.1-inch touch panel on top of a TFT-LCD panel. With the proposed touch readout circuit, the signal-to-noise ratio (SNR) is improved by up to 13.1 dB compared to the conventional touch readout circuit using single-ended amplifiers.

A novel-16–60 V input common-mode voltage current-shunt monitor

This paper presents an effective design solution for current-shunt monitor (CSM) adapting to both positive and negative power supply applications, where the supply voltage is input common-mode voltage (CMV) of CSM ranged from −16 to 60 V. The proposed CSM mainly consists of a high-voltage low-drop output (HVLDO) regulator, a CSM core, and a 2nd-stage gain generator. The HVLDO regulator converts the independent supply voltage (5-16 V) to a stable internal output supply voltage of 5 V for other consequent circuits. The proposed CSM core adopts a fully-differential amplifier, a single-ended output amplifier, current-mirror transistors, and several resistors to constitute a stable negative feedback system. Due to its stable operation, the CSM core with both positive and negative CMV can successfully detect drops across the shunt resistor. The 2nd-stage generator is used to achieve a higher gain. By selecting proper transistor and resistor size in both CSM core and 2nd-stage gain generator, a total scaled gain of 100 V/V is achieved in this study. The proposed CSM architecture has been successfully implemented in a 0.25μm Bipolar-CMOS-DMOS (BCD) technology, and the area is around 1.44 mm2. Measurements show that the proposed CSM with an input CM voltage ranged from -16–60 V can sense an input voltage difference 4–16 mV.

A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET

The world’s first 5-carrier aggregation (CA) supporting digital-intermediate frequency (IF) receiver (RX) to support 5G sub-6 GHz new radio (NR) and CA/E-UTRA NR dual connectivity (CA/EN-DC) maintaining 2G and 3G in 14-nm FinFET CMOS technology is presented. Three digital-IF RXs with a shared local oscillator-phase-locked loop (LO-PLL) are integrated for supporting inter-/intra-band 5-CA to reduce power consumption and area of the massive number of RX paths. The RX features nine single-ended low-noise amplifiers (LNAs) with low/mid/high band (L/M/HB) characteristics. It achieves noise figure (NF) of 1.5 dB with 18 dB external LNA gain and +7.6-dBm out-of-band (OOB) input intercept point 3 (IIP3), and input intercept point 2 (IIP2) calibration is not required thanks to IF planning. The RX achieves an error vector magnitude (EVM) of 2.5% by intra-4CA for B1 LTE10MHz and LTE20MHz in one single RX path, as well as inter-3CA for B3, B5, and B7 long-term evolution (LTE) 20 MHz with a shared LO-PLL. The estimated power saving by sharing a single LO-PLL is 17% compared to 3-CA RXs with three separate LO-PLLs.

A novel voltage-mode universal second-order filter using five single ended OTAs and its quadrature sinusoidal oscillator application

This study proposes a single-ended operational trans-conductance amplifier (SEOTA)-based triple inputs and single output high-input impedance voltage-mode (VM) universal second-order filter. The proposed universal VM SEOTA-based second-order filter can be realized for the non-inverting low-pass, non-inverting high-pass, non-inverting band-reject, non-inverting all-pass and inverting band-pass filtering functions by appropriately using different triple-input voltage signals. The high-input impedances of the proposed universal VM SEOTA-based configuration enable the second-order filter to be cascaded without additional buffers. The proposed configuration does not employ external resistors and accordingly is an active SEOTAs and capacitors (SEOTA-C) universal second-order filter. The proposed circuit using two grounded capacitors which is more apposite to further develop into an integrated circuit implementation. The resonance angular frequency and quality factor are orthogonal electronically adjustable. By slightly modifying the proposed universal VM SEOTA-based second-order filter configuration, the VM SEOTA-C quadrature sinusoidal oscillator is achieved. The oscillation frequency and the oscillation condition of the quadrature sinusoidal oscillator can be independently and electronically tuned by adjusting the bias currents of two SEOTAs. PSpice simulation results confirmed theoretic anticipation. The result of the experiment of the commercially available SEOTAs, LT1228s, are also used to verify the characteristics of the proposed universal VM SEOTA-based second-order filter and VM SEOTA-based quadrature sinusoidal oscillator.

Size Constraint to Limit Interference in DRL-Free Single-Ended Biopotential Measurements

In this work, it is shown that small, battery-powered wireless devices are so robust against electromagnetic interference that single-ended amplifiers can become a viable alternative for biopotential measurements, even without a Driven Right Leg (DRL) circuit. A power line interference analysis is presented for this case showing that this simple circuitry solution is feasible, and presenting the constraints under which it is so: small-size devices with dimensions less than 40 mm × 20 mm. A functional prototype of a two-electrode wireless acquisition system was implemented using a single-ended amplifier. This allowed validating the power-line interference model with experimental results, including the acquisition of electromyographic (EMG) signals. The prototype, built with a size fulfilling the proposed guidelines, presented power-line interference voltages below 1.2 µVPP when working in an office environment. It can be concluded that a single-ended biopotential amplifier can be used if a sufficiently large isolation impedance is achieved with small-size wireless devices. This approach allows measurements with only two electrodes, a very simple front-end design, and a reduced number of components.

A simple architecture for high performance class-D audio amplifier with novel RC network as negative feedback loop

<span>In this work, we have designed and simulated a proposed architecture and good performances single-ended class-D audio amplifier (CDA). The proposed circuit is build using pulse-width modulation (PWM). We have proposed a novel RC network as negative feedback loop attached to a second-order integrator to get free of high-frequency carrier ripples and to reach improved output accuracy, thus improved performance and efficiency. This proposed negative feedback loop extremely reduces total harmonic distortion plus noise (THD+N). We have used a passive second-order butterworth output filter. This circuit fulfills a power supply rejection ratio (PSRR) of 75 dB, a THD+N of 0.004%, 3 times less than attained by usual feedback loop. The proposed circuit with quiescent current of 0.02 mA, signal to noise ratio (SNR) of 89 dB, and peak efficiency of 90% is running at 400 kHz switching frequency. The results of simulation demonstrate that this circuit significantly keeps up with the performance of other circuits but taking advantage of its simple architecture.</span>

High‐efficiency broadband power amplifier design via ideal de‐embedding and direct compensation of GaN‐HEMTs parasitics

In this work, a design approach for broadband high-efficiency power amplifiers is presented. The proposed technique is based on deductive de-embedding of the nonlinear parasitics of packaged GaN-HEMT devices. A new transistor parasitics equivalent network is proposed that utilises a model-based extraction flow. A simple two-element compensation network is then used to accurately compensate the extracted nonlinear device parasitics; this enables optimum load resistance to be presented to the device current generator using a real-to-real matching network. In order to validate the proposed concept, a single-ended Class-AB power amplifier is designed and fabricated using a Wolfspeed 25-W GaN HEMT ‘CGH40025F’ transistor. At a centre frequency of 2.35 GHz, a fractional bandwidth of 55% is achieved. The measured average drain efficiency and power gain of the designed power amplifier are 71% and 10.4 dB, respectively.

Schmitt trigger based single-ended voltage amplifier for ultra-low-voltage supplies

Schmitt trigger based single-ended voltage amplifier for ultra-low-voltage supplies

A low noise CMOS instrumentation amplifier for TMR-effect-based magnetic sensors

This paper presents a low [Formula: see text] noise CMOS single-ended output instrumentation amplifier (IA) for tunneling magnetic resistance (TMR) sensors. For high DC gain and linearity, the amplifier employs three-stage current-feedback topology. For high CMRR and PSRR, the first two stages employ fully differential input. To maintain stability and lower the power dissipation, the amplifier employs trans-conductance with capacitance feedback compensation (TCFC) topology. The amplifier employs chopping technology and continuous-time AC-coupled ripple reduction loop to reduce [Formula: see text] noise and chopping ripple. The whole chip is fabricated using 0.35 [Formula: see text]m CMOS-BCD technology and the total area is 1 mm2. Test result shows an input-referred noise power spectral density (PSD) of 14 nV/[Formula: see text] is achieved with 1 Hz [Formula: see text] corner. The bandwidth is larger than 50 kHz [Formula: see text] with 20 pF load capacitor. The total current is 300 [Formula: see text]A at 5 V supply.

Self-Biased and Supply-Voltage Scalable Inverter-Based Operational Transconductance Amplifier with Improved Composite Transistors

This paper deals with a single-stage single-ended inverter-based Operational Transconductance Amplifiers (OTA) with improved composite transistors for ultra-low-voltage supplies, while maintaining a small-area, high power-efficiency and low output signal distortion. The improved composite transistor is a combination of the conventional composite transistor and forward-body-biasing to further increase voltage gain. The impact of the proposed technique on performance is demonstrated through post-layout simulations referring to the TSMC 180 nm technology process. The proposed OTA achieves 54 dB differential voltage gain, 210 Hz gain–bandwidth product for a 10 pF capacitive load, with a power consumption of 273 pW with a 0.3 V power supply, and occupies an area of 1026 μm2. For a 0.6 V voltage supply, the proposed OTA improves its voltage gain to 73 dB, and achieves a 15 kHz gain–bandwidth product with a power consumption of 41 nW.

A 28-GHz Doherty Power Amplifier With a Compact Transformer-Based Quadrature Hybrid in 65-nm CMOS

This brief presents a single-ended, two-stage, and symmetric Doherty power amplifier (DPA). A rigorous and closed-form formula is proposed to design the transformer-based quadrature hybrid. The hybrid combines the advantages of flexibility, compactness, and low loss. A non-classic Doherty impedance inverting network is co-designed with the input network for phase matching. Besides, the parasitic parameters of the interconnects and RF pads are used to reduce the value of the inductor in the LC network. Designed and implemented in a 65-nm CMOS process, the fully integrated compact DPA prototype occupies only 0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. The experimental prototype operating at 28 GHz achieves 18.7 % power-added efficiency (PAE) at 6-dB power back-off (PBO). A maximum small-signal gain of 20.4 dB is achieved with a -3-dB bandwidth from 25.6 to 29.4 GHz. A saturated output power ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ) of 17.5 dBm is measured with the peak PAE of 27%. At 6-dB PBO, the DPA prototype increases the efficiency by 2.8 and 1.4 times over a normalized Class-B and Class-A PA, respectively.

Nonlinear distortion of angle modulation signal in output power amplifiers

The output power amplifier is operated in nonlinear mode to increase its efficiency, at which the signal is distorted more. The goal is to analyze effects of nonlinearity on the modulating signal of angle-modulated signal distortions for single-ended and push-pull output power amplifiers with memory and without it. The amplifier characteristic ic(vBE) is preset by the cubic polynomial. The output voltage of memoryless amplifier uout(t) is found by Ohm's law. And in case with amplifier with memory, the output voltage uout(t) is found by Complex amplitude method with a Fourier series of function ic(t). The output voltage uout(t) is represented as the narrowband process with envelope of the waveform U1(t) and initial phase Ф1(t) to determine the angular modulation law Ф1(t) at the amplifier output. The function U1(t) is defined as combination of in-phase А(t) and quadrature В(t) components. The distortion estimate based on Total Harmonic Distortion (THD). The measurement of THD is defined as the ratio of the RMS amplitude of a set of higher harmonic frequencies to the RMS amplitude of the first harmonic. The spectrum of function Ф1(t) is represented a Fourier series. In single-ended memoryless amplifier and non-cutoff mode, the THD decreases as m increases and THD of modulating signal is {37.6; 18.8; 6.3%} at m {0.5; 1; 3}. In cutoff mode, the smallest THD is {15.18; 5.13%} at m {1; 3} as θ = 140o. In push-pull memoryless amplifier and θ = 90o, the THD is {22.2; 11.1; 3.7%} at m {0.5; 1; 3} which is 1.7 times less than in a single-ended amplifier without cutoff. This is due to compensation even-order harmonic of amplified signal at the output of a pushpull amplifier. In this case of memoryless amplifier, the transistor load is a parallel RLC circuit. The distortion decreases under m increases at first (up m is 1.5), but then rapidly increases (from m is 1.7). This is due to increase of the parasitic harmonics level caused by the nonlinearity of the phase-frequency characteristic of RLC circuit. The calculations show that THD of modulating signal is 3.35, 9.02 and 22.88 % at Q = 10 and m {0.5; 1; 3}, respectively. In cutoff mode, the smallest THD is at θ = 90o and it does not depend on θ at large values of m. In push-pull amplifier with memory, the THD is 2.8, 2.5 and 3.0 times less than for a singleended amplifier without cutoff at Q {2.5; 5; 10}, respectively. The results of this paper can be used for the design of signal processing systems.

A Broadband 110–170-GHz Stagger-Tuned Power Amplifier With 13.5-dBm P sat in 130-nm SiGe

This letter presents a fully integrated three-stage single-ended D-band power amplifier (PA) designed in 0.13-μm silicon-germanium (SiGe) BiCMOS technology. Several bandwidth extension techniques and matching networks are mutually exploited to maximize Bandwidth (BW) performance while assuring unconditional stability. Its measured 3-dB bandwidth covers the entire D-band (110-170 GHz). The PA has a small-signal peak gain of 21 dB at 151 GHz. Its saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) in the D-band varies from 11.8 to 13.9 dBm and its output referred 1-dB compression point (OP1 dB) from 9.2 to 12.5 dBm within the D-band. The presented amplifier occupies 0.65 × 0.47 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (including pads) and draws a current of 115 mA from a 3.3-V supply. To the best of our knowledge, these performances represent the state of the art in silicon technology with a minimum (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 11.8 dBm and (OP1 dB) of 9.2 dBm covering the entire D-band.

Post-Voltage-Boost Circuit-Supported Single-Ended Class-B Amplifier for Piezoelectric Transducer Applications.

Piezoelectric transducers are important devices that are triggered by amplifier circuits in mobile ultrasound systems. Therefore, amplifier performance is vital because it determines the acoustic piezoelectric transducer performances. Particularly, mobile ultrasound applications have strict battery performance and current consumption requirements; hence, amplifier devices should exhibit good efficiency because the direct current (DC) voltage in the battery are provided to the supply voltages of the amplifier, thus limiting the maximum DC drain voltages of the main transistors in the amplifier. The maximum DC drain voltages are related with maximum output power if the choke inductor in the amplifier is used. Therefore, a need to improve the amplifier performance of piezoelectric transducers exists for mobile ultrasound applications. In this study, a post-voltage-boost circuit-supported class-B amplifier used for mobile ultrasound applications was developed to increase the acoustic performance of piezoelectric transducers. The measured voltage of the post-voltage-boost circuit-supported class-B amplifier (62 VP-P) is higher than that of only a class-B amplifier (50 VP-P) at 15 MHz and 100 mVP-P input. By performing the pulse-echo measurement test, the echo signal with the post-voltage-boost circuit-supported class-B amplifier (10.39 mVP-P) was also noted to be higher than that with only a class-B amplifier (6.15 mVP-P). Therefore, this designed post-voltage-boost circuit can help improve the acoustic amplitude of piezoelectric transducers used for mobile ultrasound applications.

Front-End Amplifiers for Tuning Forks in Quartz Enhanced PhotoAcoustic Spectroscopy

A study of the front-end electronics for quartz tuning forks (QTFs) employed as optoacoustic transducers in quartz-enhanced photoacoustic spectroscopy (QEPAS) sensing is reported. Voltage amplifier-based electronics is proposed as an alternative to the transimpedance amplifier commonly employed in QEPAS experiments. The possibility to use differential input/output configurations with respect to a single-ended configuration has also been investigated. Four different architectures have been realized and tested: a single-ended transimpedance amplifier, a differential output transimpedance amplifier, a differential input voltage amplifier and a fully differential voltage amplifier. All of these amplifiers were implemented in a QEPAS sensor operating in the mid-IR spectral range. Water vapor in ambient air has been selected as the target gas species for the amplifiers testing and validation. The signal-to-noise ratio (SNR) measured for the different configurations has been used to compare the performances of the proposed architectures. We demonstrated that the fully differential voltage amplifier allows for a nearly doubled SNR with respect to the typically used single-ended transimpedance amplifier.

Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix

This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.