Single-ended Amplifier Research Articles

A 2.4GHz Radio-Over-Fiber Laser Diode Drive Amplifier in 0.18-um CMOS<sup><sup><sup><sup></sup></sup></sup></sup>

The design of a 2.4GHz radio-over-fiber (ROF) laser diode drive amplifier using TSMC 0.18-um CMOS technology is presented in this paper. The proposed drive amplifier is a single-ended two-stage amplifier with the operating voltages of 1.8V and 3.3V. The technique of dynamic bias is employed to enhance linearity. The post simulation results show that the linear amplifier achieves the power gain of 26.26dB, the output 1dB compression point of 20.49dBm at 2.4GHz. The maximum power added efficiency (PAE) is 27.97%. The components are all on chip including the input and output matching network, and the die size is 1.065mm×0.73mm.

Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications

This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and-distortion-ratio (SNDR) of 46.7 dB at Pin = ?6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/?0.5 and +0.2/?0.5 LSB, respectively. The ADC power consumption is 300 μW and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well.

A design method for active high-CMRR fully-differential circuits

A simple method for designing instrumentation fully-differential (FD) circuits based on standard single-ended (SE) operational amplifiers (OAs) is presented. It departs from a SE prototype that verifies the desired differential-mode transfer function, thereby leading to FD versions of the circuit. These circuits have a high common mode rejection ratio (CMRR), independent of component imbalances, and a unity common-mode gain. The proposed method does not allow the design of common-mode response, but it does verify common-mode stability, thus ensuring stable FD circuits. It is intended for instrumentation applications in which high CMRRs are required. The proposed approach makes it possible to design and implement inverter and non-inverter topologies as well. Design examples and experimental data are presented. Using general-purpose OAs and 5%-tolerance components, the CMRR of these circuits easily exceeds 90 to 100 dB.

A Multichannel EEG Acquisition Scheme Based on Single Ended Amplifiers and Digital DRL

Single ended (SE) amplifiers allow implementing biopotential front-ends with a reduced number of parts, being well suited for preamplified electrodes or compact EEG headboxes. On the other hand, given that each channel has independent gain; mismatching between these gains results in poor common-mode rejection ratios (CMRRs) (about 30 dB considering 1% tolerance components). This work proposes a scheme for multichannel EEG acquisition systems based on SE amplifiers and a novel digital driven right leg (DDRL) circuit, which overcome the poor CMRR of the front-end stage providing a high common mode reduction at power line frequency (up to 80 dB). A functional prototype was built and tested showing the feasibility of the proposed technique. It provided EEG records with negligible power line interference, even in very aggressive EMI environments.

Integrated CMOS RF transmitter with a single-ended power amplifier

This article presents a highly integrated CMOS RF double-sideband (DSB) transmitter (TX) including an active input balun and a single-ended power amplifier (PA) for a ultrahigh frequency radiofrequency identification (RFID) system-on-chip reader. The conventional TX architecture, including an up-conversion mixer and a balanced PA, requires an output balun to create the needed single-ended load. Compared to the conventional TX architecture, the proposed system provides a more compact circuit and uses a smaller chip area because the active balun and the single-ended PA have a much smaller size than those using a passive balun and a differential PA. In addition, the gain of the active balun, which is generally larger than unity, can be a benefit in the system design budget. The designed TX IC is fabricated using a 0.13 μm CMOS process on a small area of 780 × 560 μm2 (including pads). The TX IC exhibited an overall conversion gain of 41.7 dB, an output P1dB of 18 dBm, an OIP3 of 28 dBm, a DSB noise figure of 14.8 dB, and a power consumption of 284.4 mW, including the 42.9 mW consumed by the local oscillator buffer stages. The implemented TX IC complied with the spectral mask for the DSB amplitude-shift keying signal of the RFID reader at an output power of 15.5 dBm. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:205–210, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27257

A single-to-differential low-noise amplifier with low differential output imbalance

This paper presents a single-ended input differential output low-noise amplifier intended for GPS applications. We propose a method to reduce the gain/amplitude and phase imbalance of a differential output exploiting the inductive coupling of a transformer or center-tapped differential inductor. A detailed analysis of the theory of imbalance reduction, as well as a discussion on the principle of choosing the dimensions of a transformer, are given. An LNA has been implemented using TSMC 0.18 μm technology with ESD-protected. Measurement on board shows a voltage gain of 24.6 dB at 1.575 GHz and a noise figure of 3.2 dB. The gain imbalance is below 0.2 dB and phase imbalance is less than 2 degrees. The LNA consumes 5.2 mA from a 1.8 V supply.

Hierarchical sizing and biasing of analog firm intellectual properties

A hierarchical sizing and biasing methodology for analog firm intellectual properties (IPs) is presented. An analog firm IP designates an unsized transistor netlist of an analog circuit. The methodology sizes and biases an analog firm IP by automatically generating suitable sizing procedures. The generated procedures respect topology constraints, designer's hypotheses and design constraints. The procedures are represented using dependency graphs. The methodology deals with different aspects of analog design problems such as MOS inversion level control, insufficient or excess design parameters, systematic offset and negative-feedback. Its application in both fields of analog synthesis and simulation is outlined. The proposed methodology has been successfully used to size, bias and analyze two analog IPs: a single-ended two-stage operational amplifier and a fully differential transconductor. This is performed using 130nm CMOS technology with VDD=1.2V. The results prove the effectiveness and precision of the proposed methodology.

A Broadband Low-Power Low-Noise Active Balun With Second-Order Distortion Cancellation

This paper presents a broadband single-ended input differential output low noise amplifier exploiting IM2 cancelling. A linear feedback from the common mode output to the single-ended input effectively cancels the second-order distortion products in the differential output. The feedback path can be designed for minimum noise, leading to equal or lower noise compared to the amplifier without feedback. A replica bias ensures reduced sensitivity to process, supply voltage and temperature variations. The measured IIP2 across the band from 230 MHz to 470 MHz, varies from 19 to 26 dBm when the feedback is disabled and from 28 to 34 dBm when the feedback is enabled. Measured NF is 2.25 dB in the VHF band and between 2 and 4 dB in the UHF band. Power dissipation is 7.8 mW .

A single-ended CMOS chopper amplifier for 1/f noise reduction of n-channel MOS transistors

This paper describes a single-ended CMOS chopper amplifier for 1/f noise reduction of n-channel MOS transistors and its application to a low-noise high-gain switched-capacitor (SC) amplifier for sensor interface circuits. Since the chopping is used inside of the operational transconductance amplifier (OTA), this amplifier can be used for high output impedance sensors. To investigate the effect of the proposed chopping technique, a test chip was fabricated using 0.25µm mixed-signal CMOS process. The total input-referred noise is greatly reduced by using a high chopping frequency of 256kHz to 20µVrms from 295µVrms without chopping.

A design method for active high-CMRR fully-differential circuits

A simple method for designing instrumentation fully-differential (FD) circuits based on standard single-ended (SE) operational amplifiers (OAs) is presented. It departs from a SE prototype that verifies the desired differential-mode transfer function, thereby leading to FD versions of the circuit. These circuits have a high common mode rejection ratio (CMRR), independent of component imbalances, and a unity common-mode gain. The proposed method does not allow the design of common-mode response, but it does verify common-mode stability, thus ensuring stable FD circuits. It is intended for instrumentation applications in which high CMRRs are required. The proposed approach makes it possible to design and implement inverter and non-inverter topologies as well. Design examples and experimental data are presented. Using general-purpose OAs and 5%-tolerance components, the CMRR of these circuits easily exceeds 90 to 100 dB.

Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

52–75 GHz wideband low-noise amplifier in 90 nm CMOS technology

A three-stage single-ended low-noise amplifier covering almost the entire V-band is presented. The design employs three cascade single-ended stages with pi-sections for wideband interstage matching and source degeneration at the first stage. The amplifier achieves a peak gain of 14 dB and minimum noise figure of 4.8 dB. A record 3 dB bandwidth of 37 is achieved with power consumption of 32 mW and core silicon area of 0.065 mm 2 in 90 nm CMOS technology.

A read-decoupled gated-ground SRAM architecture for low-power embedded memories

In this work, a gated ground SRAM architecture based on a seven transistor (7T) bit-cell is proposed. The proposed cell shows higher data stability and yield under varying process, voltage, and temperature (PVT) conditions than the conventional 6T cell. A single-ended sense amplifier is also presented to read from the proposed cell while a unique write mechanism is used to reduce the write power to less than half of the write power of the 6T cell. The proposed cell consumes similar silicon area and leakage power as the 6T cell when laid out and simulated using a commercial 65-nm CMOS technology. The ground gating is done by selectively controlling the column virtual ground (CVG) of accessed word in a row. This significantly reduces the leakage power consumption and enables implementing multiple words per row, which lowers multiple-bit data upset in the event of radiation induced single event upset or soft error. In addition, the proposed cell inherently has a 30% larger soft error critical charge, making its soft error rate (SER) less than the half of that of the 6T cell.

A CMOS MedRadio Receiver RF Front-End With a Complementary Current-Reuse LNA

An ultra-low-power 401-406-MHz Medical Device Radiocommunications Service receiver RF front-end for biomedical telemetry applications is implemented using 0.18-μm CMOS technology. A single-ended complementary current-reuse low-noise amplifier (CCRLNA) is proposed that achieves a power gain of 20 dB, noise figure (NF) of 2.8 dB, IIP3 of -8.1 dBm, and second-order intercept point of +34 dBm while consuming only 150 μW at 1-V supply voltage. The total receiver RF front-end, including the proposed CCRLNA, in-phase/quadrature folded mixers, and local oscillator buffers, achieves a conversion gain of 28.7 dB, NF of 5.5 dB, and third-order intercept point of -25 dBm while consuming less than 500 μW from a 1-V supply voltage and occupying 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of core die area.

Differential Noise Figure De-Embedding: A Comparison of Available Approaches

A new matrix-based approach for de-embedding the noise figure of a differential device has been recently presented. In this paper, an enhancement to this method will be provided. The new method will be compared to state-of-the-art approaches. For comparison, measurements have been performed on an amplifier with distinct transfer characteristics. The respective integrated circuit is composed of two single-ended amplifiers placed in close proximity within the layout. Due to capacitive cross-couplings arising from this arrangement, the differential noise figure is degraded compared to the single-ended one, which indicates the requirement of differential excitation. For completion, measurements have also been performed on a differential device. A commercially available evaluation board has been used for this purpose and measurement results agree well with those specified by the manufacturer.

A BiCMOS single ended multiband RF-amplifier and mixer with DC-offset and second order distortion suppression

Direct conversion receivers are widely used for full duplex mobile radio communication systems. This paper describes a novel SAW-less single-ended RF amplifier connected to a single-ended mixer with a feedback loop that suppresses the second-order distortion from TX cross modulation of the LO-leakage as well as DC-offset at the mixer output. In Monte Carlo simulations the design achieves +47 dBm minimum IIP2 with 32 dB conversion voltage gain. The advantage with the proposed architecture is that it is fully single-ended. Especially in multiband integrated radios this is highly desirable since the pin-count for the LNAs is reduced by half. The PCB routing of the RF input signal is simplified. The design requires two off-chip filter capacitors of non critical value intended to be placed on the laminate inside the package.

Amplitude-modulation characteristics of power-combining Class-E amplifier with finite choke

Power back-off performances of a new variant power-combining Class-E amplifier under different amplitude-modulation schemes such as continuous wave (CW), envelope elimination and restoration (EER), envelope tracking (ET) and outphasing are for the first time investigated in this study. Finite DC-feed inductances rather than massive RF chokes as used in the classic single-ended Class-E power amplifier (PA) resulted from the approximate yet effective frequency-domain circuit analysis provide the wherewithal to increase modulation bandwidth up to 80% higher than the classic single-ended Class-E PA. This increased modulation bandwidth is required for the linearity improvement in the EER/ET transmitters. The modified output load network of the power-combining Class-E amplifier adopting three-harmonic terminations technique relaxes the design specifications for the additional filtering block typically required at the output stage of the transmitter chain. Qualitative agreements between simulation and measurement results for all four schemes were achieved where the ET technique was proven superior to the other schemes. When the PA is used within the ET scheme, an increase of average drain efficiency of as high as 40% with respect to the CW excitation was obtained for a multi-carrier input signal with 12 dB peak-to-average power ratio.

Inverter-based 1 V analog front-end amplifiers in 90 nm CMOS for medical ultrasound imaging

In this paper, we present the design and experimental evaluation of 1 V analog front-end amplifiers designed in 90 nm CMOS technology for capacitive micro-machined ultrasound transducers (CMUTs) for medical ultrasound imaging systems. We propose two front-end amplifier topologies based on an inverter-based cascode amplifier; the first is a continuous time amplifier and the second is a charge sampling amplifier (CSA). The proposed front-end amplifiers are designed to amplify the signals from CMUTs in the frequency bandwidth from 15 to 45 MHz with a centre frequency of 30 MHz. From the measurements, the continuous time single-ended transimpedance amplifier achieves a voltage gain of 19 dB, an output noise power spectral density of 0.042 (μV)/SQRT(Hz) at a centre-frequency of 30 MHz, and a total harmonic distortion of −23 dB at 450 mV p–p output voltage at 30 MHz input signal frequency. It draws only 598 μA per amplifier from a 1 V power supply. Its area measured only about 32 μm × 32 μm per amplifier. On the other hand, a sampling based front-end amplifier [CSA] achieves a transfer gain of 17.4 dB at an input signal frequency of 30 MHz and an upper 3 dB cut-off frequency of 46 MHz at a sampling clock frequency of 100 MHz. It consumes 586 μA per amplifier from a 1 V power supply and achieves a signal-to-noise (SNR) ratio of 45.7 dB with a peak-to-peak output signal amplitude of 500 mV at a sampling frequency of 100 MHz. It occupies an area of 1470.2 μm2 (which is equivalent to 38 μm × 38 μm), which also includes the area of the switches for the CSA that will be used for the single CMUT element.

A Subharmonic Receiver in SiGe Technology for 122$~$GHz Sensor Applications

The iterative design of an integrated subharmonic receiver for 120-127 GHz is presented. The receiver consists of a single-ended low-noise amplifier (LNA), a push-push voltage-controlled oscillator (VCO) with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 255 GHz/315 GHz. In the first design the differential down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure (NF) is 11 dB. The 3 dB bandwidth reaches from 125 GHz to 129 GHz. The input 1 dB compression point is at - 40 dBm. The receiver draws 139 mA from a supply voltage of 3.3 V. A subsequent design demonstrates 31 dB differential gain at 122 GHz, and 11 dB NF. The 3 dB bandwidth is from 121 GHz to 124 GHz. The receiver has a NF of 8 dB for 3 GHz IF frequency due to integrated RF bandpass-filtering. It is realized by the lower NF of the LNA, and the LNA itself.

An efficient CMOS power-combining technique with differential and single-ended power amplifier

This article proposes an efficient power-combining architecture with differential and single-ended power amplifiers (PAs) in a CMOS process. The single-ended amplifier is added for overall efficiency enhancement. To demonstrate this concept, a CMOS PA using the proposed architecture was fabricated with a 0.13-μm CMOS technology that delivers 30.6 dBm of output power with 42% drain efficiency and 38% power-added efficiency at 1.95 GHz. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2214–2217, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25460