Hierarchical sizing and biasing of analog firm intellectual properties

Abstract

A hierarchical sizing and biasing methodology for analog firm intellectual properties (IPs) is presented. An analog firm IP designates an unsized transistor netlist of an analog circuit. The methodology sizes and biases an analog firm IP by automatically generating suitable sizing procedures. The generated procedures respect topology constraints, designer's hypotheses and design constraints. The procedures are represented using dependency graphs. The methodology deals with different aspects of analog design problems such as MOS inversion level control, insufficient or excess design parameters, systematic offset and negative-feedback. Its application in both fields of analog synthesis and simulation is outlined. The proposed methodology has been successfully used to size, bias and analyze two analog IPs: a single-ended two-stage operational amplifier and a fully differential transconductor. This is performed using 130nm CMOS technology with VDD=1.2V. The results prove the effectiveness and precision of the proposed methodology.