A watermarking technique for hard IP protection in post-layout design level

Abstract

The intellectual property (IP)-reuse-based SOC design methodology has become the mainstream. However malice modification of IP is badly infringing the expansion of legal IP- trade. Consequently the IP copyright protection becomes very sensitive and urgent. Among all kinds of IP protection (IPP) techniques, the watermarking is one of the most developed and promising approaches. In this paper we introduce a new watermarking technique for hard IP protection by embedding additional design constraints in post-physical layout design level. It can be applied to both VLSI designs and full-custom designs. In this paper, we focus on the application of this IPP approach in full-custom ones. The principle and a watermarking implementation system are proposed, and the experimental results are reported.