SIMOX Wafers Research Articles

Analysis of buried oxide layer formation and mechanism of threading dislocation generation in the substoichiometric oxygen dose region

The structure of SIMOX wafers implanted at 180 keV with doses of 0.1 × 1018-2.0 × 101816O+ cm−2 at 550 °C, followed by annealing over the temperature range of 1050–1350 °C, has been investigated using cross-sectional transmission electron microscopy and a chemical etching. With doses of 0.35 × 1018-0.4 × 1018 cm−2, a continuous buried oxide layer having no Si island inside is formed by high-temperature annealing at 1350 °C. At a dose of 0.7 × 1018 cm−2, multilayered oxide striations appear in the as-implanted wafer. These striations grow into multiple buried oxide layers after annealing at 1150 °C. The multiple layers lead to a discontinuous buried oxide layer, resulting in the formation of a number of Si micropaths between the top Si layer and the Si substrate when the wafer is annealed at 1350 °C. These Si paths cause the breakdown electric field strength of the buried oxide layer to deteriorate. With doses of 0.2 × 1018-0.3 × 1018 cm−2 and of higher than 1.3 × 1018 cm−2, an extremely high density of threading dislocations is generated in the top Si layer after annealing at 1350 °C. The dislocation density is greatly reduced to less than 103 cm−2 when the oxygen dose falls in the range of 0.35 × 1018-1.2 × 1018 cm−2. Here we propose a mechanism that accounts for the threading dislocation generation at substoichiometric oxygen doses of less than 1.2 × 1018 cm−2.

Quality of gate oxides grown on state-of-the-art SIMOX and ZMR SOI substrates

The quality of 25-nm gate oxides formed on state-of-the-art SIMOX and ZMR silicon-on-insulator (SOI) substrates was studied using NMOSFETs. Circular, edgeless, and conventional island isolated devices were used. Devices fabricated on bulk silicon wafers were studied for comparison. I-V characteristics, breakdown voltages, charge trapping, and charge to breakdown were characterized. The results clearly demonstrated that the quality of SIMOX and ZMR wafers and especially of the top Si surface was as good as that of bulk silicon. The quality of the gate oxides formed on island isolated devices was poor due to defective oxide formed on the sidewalls. A comparison of circular, edgeless MOSFETs and island isolated MOSFETs can be used to optimize island etching, sidewall cleaning, and gate oxidation processes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Formation of stacking-fault tetrahedra in low defect density oxygen-implanted silicon-on-insulator material

Fabrication of integrated circuits on SOI (Silicon-On-Insulator) material is very attractive because it offers high component density, immunity to latch-up and radiation hardness. Among various SOI techniques SIMOX Separation by IMplantation of OXygen) provides the best material, with carrier mobilities and defect densities approaching bulk silicon values, Early SIMOX wafers were implanted at temperatures below 600°C and annealed at high temperature (&gt;1300°C), which gave a high defect density (109cm−2), including threading dislocations and narrow stacking faults (SFs), as shown in Figure 1. Higher temperature (&gt;600°C) implantation of SIMOX reduced defect densities to 106cm-2 with pairs of narrow SFs in the top silicon layer, as shown in Figure 2. This paper describes a further reduction of defect density in SIMOX material through various annealing conditions, which has resulted in a defect density less than 105cm−2. A new formation mechanism for stacking fault tetrahedra is also discussed.Silicon (100) wafers were sequentially implanted (620°C) and annealed (at 1320°C for 5 hours) to doses of 0.5, 0.5, and 0.8×l018cm-2.

A hardened technology on SOI for analog devices

A hardened and mixed analog-digital technology under development is presented. This technology currently includes a PJFET with a good hardness and CMOS transistors with a potential multi-megarad hardness. First tests of bipolar transistors with a not yet optimized structure (structure of the JFET) are discussed. The feasibility of a PJFET with a 1.2- mu m-thick active layer on top of a SIMOX wafer with a very good immunity to radiation has been shown. A highly doped buried layer has been successfully introduced into the process, even if some spreading of that layer must be taken into account to adjust the threshold voltages. This buried layer is able to screen any charge in the buried oxide from the active layer even after several tens of megarads. The neutron analysis of nonoptimized bipolar transistors gives confidence in the achievement of good quality and hardened transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Relaxed Si1−xGex Layers on Simox Avoiding a Lattice Mismatched Heterointerface

ABSTRACTFor the first time, Si1 xGex layers on amorphous SiO 2 were produced by modification of the Si surface layer of a SIMOX wafer. We used two alternative methods. An additional Si1.. Gey layer was deposited epitaxially on a SIMOX wafer followed by rapid thermal annealing. Diffusional intermixing of the layers produced a homogeneous Si1 xGex layer on SiO 2. In a second attempt, Ge was implanted into the Si surface layer and thermally treated. In both cases epitaxial Si1 xGex layers on SiO2 with minimum yield values around 9% were obtained. Rutherford backscattering and cross sectional transmission electron microscopy were used to characterize the new structures.

Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of +or-150 AA was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Back channel uniformity of thin SIMOX wafers

Thin top silicon layers ranging from 90-150 nm were prepared by oxidation and etch back of SIMOX wafers. These wafers were implanted at 200 keV with oxygen doses ranging from 1.8*10/sup 18/ cm/sup -2/ to 2.5*10/sup 18/ cm/sup -2/ followed by a high temperature anneal. The back channel threshold voltage uniformity of these undoped thin silicon SIMOX wafers were evaluated by a new point contact transistor technique. Differences in annealing ambients may be the source of improved back channel uniformity as observed by the point contact transistor characterization technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Oxygen rich SIMOX?

18O(200 keV, 2.0*1017 cm-2) has been implanted at 6 K into an 'as implanted' SIMOX wafer (silicon implanted with 16O at 200 keV, 1.8*1018 cm-2 and 500 degrees C). In situ Rutherford backscattering measurements at 6 K, 77 K and room temperature indicate approximately 15% excess oxygen above the stoichiometric value for SiO2 in the buried-oxide layer. Additional room-temperature measurements were carried out off-line by infrared and secondary ion mass spectrometries. A comparison of the original SIMOX material with the sample implanted with 18O at 6 K leads to the conclusion that during warm up the 18O concentration depth profile remains essentially unchanged with the maximum total concentration remaining above the original 16O value. The infrared measurements indicate that all of the oxygen atoms are bound to silicon atoms.

Microscope-spectrophotometric analysis to determine the origins of the colour variations on SIMOX wafers

Reflectance measurements using microscope-spectrophotometry have been undertaken to determine the origin of the colour rings on SIMOX wafers. When these measurements are correlated with the results from cross sectional transmission electron microscopy (XTEM) and secondary ion mass spectrometry (SIMS) it is found that normal incidence reflectance is extremely sensitive and closely related to changes m the microstmcture of the specimen. In addition, the increasing transparency of silicon to visible light, with increasing wavelength, means that the structure can be effectively probed to different depths, simply by changing the wavelength. These data have been used to establish optical models which enable the computed data to be fitted with the experimental measurements, and vice versa. Thus the microstructure of a SIMOX specimen may be predicted simply from the dispersion of its reflectance. As this is a fast and contactless technique it has potential applications for the nondestructive testing and mapping of SIMOX substrates.

SIMOX wafers with low dislocation density produced by a 100-mA-class high-current oxygen implanter

The dislocation density and the structure of SIMOX wafers formed under different implantation conditions have been investigated using Secco etching and cross-sectional transmission electron microscopy (XTEM). The relationship between the breakdown voltage of the buried oxide layer and the oxygen dose has also been studied. The dislocation density decreases as the dose decreases and the wafer temperature, during implantation, increases. The SIMOX wafer implanted at 180 keV with a low dose of 0.4 × 10 18 cm −2 at 550°C and subsequently annealed at temperatures higher than 1300°C has an extremely low dislocation density on the order of 10 2 cm −2. The buried oxide layer of this SIMOX wafer has a breakdown voltage of 40 V.

SIMOX-material quality in a semi-industrial production

Based on the results of five years of research on the SIMOX process, a complete facility for production of SIMOX wafers on a semi-industrial basis has been set up at LETI. This facility which is located in a class-100 clean room comprises an BATON NV 200 implanter, a high-temperature annealing furnace and nondestructive characterization tools. As-implanted wafers are characterized from the point of view of particles, implanted oxygen dose and dose homogeneity. After annealing, the silicon overlayer thickness and homogeneity are measured. Destructive characterization tools such as nuclear reaction analysis (NRA) for absolute oxygen-dose monitoring and secondary-ion mass spectrometry (SIMS) for metallic-impurity controls are also used. TEM and XTEM are used to monitor the dislocation density and the Si/SiO 2 interface quality. The SIMOX wafers have typically a 200 nm thick silicon layer on top of a 380 nm thick buried oxide and a dislocation density smaller than 5×10 5 cm −2. This facility is also used for research on SIMOX material, with a view to producing very thin (< 100 nm) silicon overlayers that will be required for the future CMOS/SOI circuit generations.

Amorphisation and solid phase epitaxial regrowth of the silicon overlayer in SIMOX structures

In order to study the kinetics of amorphisation and regrowth m SIMOX material, device grade SIMOX wafers were implanted with 80 and 150 keV 28Si + ions at room temperature over the dose range 1 × 10 14 to 5 × 10 15 cm −2. Bulk silicon control samples ((100), 17 Ω cm) were implanted at the same time under similar conditions. Subsequently these samples were annealed at temperatures of up to 550° C. The regrowth kinetics were studied using 1.5 MeV H + Rutherford backscattering and channeling and in this paper a comparison of the regrowth in bulk silicon and in SIMOX is reported.

Surface morphology of oxygen-implanted wafers

The surface morphology of SIMOX wafers implanted at 180 keV with doses of 0.4–2.2 ⊠ 101816O+ cm−2 in a temperature range of 400–700 °C has been investigated using transmission electron microscopy (TEM) replica and cross-sectional TEM (XTEM) techniques. Wafer temperature during oxygen implantation strongly affects the morphology. A number of dents are formed on the surface of wafers implanted at temperatures higher than 510 °C with a dose of 1.8 ⊠ 1018 cm−2. Increasing the wafer temperature causes the dents to grow. The dents disappear by a high-temperature anneal of 1260 °C after the implantation. It is found that oxygen implantation through a 50-nm-thick screen oxide film prevents dent formation. A model explaining the dent formation and dent growth is also proposed.

Assessment of the Surface Quality of SIMOX Wafers by UV Reflectance

The surface quality of SIMOX wafers implanted under various conditions of implant temperature, voltage, and dose has been characterized in terms of surface contamination, roughness, and amorphization by UV reflectance spectroscopy.

Microstructure of high temperature annealed SIMOX wafer

High temperature annealing at 1350°C is performed for SIMOX wafers to obtain a high quality thin SOI structure. After the annealing, the buried oxide has sharp interfaces within the two lattice spacings of Si(200), and oxygen precipitates are removed from the top silicon layer. MOSFET's fabricated in the SIMOX wafer with the top silicon layer 70 nm thick exhibit a good stability of threshold voltage with channel lengths down to 0.7 μm.

Practical reduction of dislocation density in SIMOX wafers

The dislocation density in the superficial silicon layers of SIMOX wafers formed under different oxygen implantation conditions has been investigated using a Secco etching technique. An extremely low dislocation density in the order of 102 cm−2 has been obtained for wafers implanted at 180keV with a dose of 0.4 × 1018 and doses ranging from 0.9 to 1.2 × 1018O+/cm2 at a wafer temperature of 550°C followed by post-implant anneal at temperatures higher than 1300°C. The buried oxide layers of these SIMOX wafers have breakdown voltages higher than 40 V.

Monitoring of Heavy Metals in As‐Implanted Simox with Surface Photovoltage

Heavy metals in concentrations of E‐16‐E‐18 cm−3 are commonly found in SIMOX samples implanted in high current implanters (100 mA). In the present study, surface photovoltage (SPV) was used successfully to measure the heavy metal concentration in as‐implanted SIMOX. An initial correlation has been established between the minority carrier diffusion length measured on the back of a SIMOX wafer and Fe concentration measured by SIMS and spark source mass spectrometry in as‐implanted SIMOX films. A correlation between the leakage current of MOS transistors and the heavy metal contamination level as measured by SPV was established. SPV measurements are quick, nondestructive, and do not require any additional sample preparation. They can therefore be used as a QC method to monitor heavy metals in as‐implanted SIMOX layers.

SIMOX: Buried layer formation by ion implantation — Equipment and techniques

Requirements for a new semiconductor grade material to replace silicon-on-sapphire have surfaced over the past few years. A number of alternate materials have been produced, the most promising of which is SIMOX: Separation by IMplantation of OXygen. Characteristics of this sandwich-like substrate formed by high dose implantation of oxygen ions are described. In particular,the methodology is reviewed of producing a high quality silicon surface layer, an insulating silicon dioxide subsurface layer, and its interface with the bulk silicon. A 100 mA (nominal) oxygen implanter meets the immediate need for this material, and a steady supply of SIMOX wafers is now available. Design criteria for higher volume machines are considered.

On the Formation of Thick and Multiple Layer Simox Structures and their Applications

AbstractThis paper will address the formation of SIMOX structures with thick and multiple buried SiO2 layers by multiple oxygen implantation and growth of epitaxial Si by chemical vapor deposition (CVD). Our results indicate that SIMOX material can be produced with a buried layer of any thickness or with any number of distinct buried oxide layers and distinct silicon layers. Thick and double buried SiO2 layer material may be useful for high voltage isolation and electric field shielding.In addition, we have demonstrated optical waveguide action in SIMOX wafers. This suggests that in a double buried SiO2 layer system, three dimensional stacked integration of silicon waveguides is possible, including two level optical interconnects.

Surface morphology of SIMOX wafers

The surface structure of SIMOX wafers produced by a 100 mA class oxygen implanter has been investigated. Wafer temperature during implantation affects the surface morphology and thickness of the top silicon layers. The unevenness of the surface is closely related to cavities in the top silicon layers. Film thickness reduction is explained by the sublimation of SiO formed at the surface.