Silvaco TCAD Research Articles

GeSn based heterojunction double-gate tripple metal layer vertical TFET with enhanced DC and Analog/RF performance

In this article, low-bandgap material GeSn and high bandgap Si material heterojunction (GeSn/Si) based double gate triple metal layer Vertical TFET is designed and analyzed by ATLAS Silvaco TCAD simulation tool. Higher ON-state current is obtained by this device owing to (i) the usage of novel low band-gap material i.e., GeSn and (ii) Vertical tunneling as the gate overlaps the source region. The incorporation of GeSn material not only enhances the ON-state current but also improves the SS, albeit trading off the OFF-state current and ambipolar current of the device. To control the ambipolar current and OFF-state current, variation in the gate to drain overlap and auxiliary gate metal work function has been done. The impact of the gate to drain overlap and auxiliary gate workfunction variation has been studied for various electrical parameters. Further through extensive simulation analysis, optimized dimensions have been obtained. An enormously high ION/IOFF ratio of the order of 1.6 × 1012, steepest point, and average subthreshold swing of 7.5 mV/dec and 12.3 mV/dec respectively has been achieved through this proposed device. In addition to this, comparison of the proposed device with other novel TFET devices reported in literature has been done. From the comparison, it has been concluded that better results are obtained by the proposed device in terms of ION, IAMB, ION/IOFF ratio, SSavg, and gm. Therefore, this novel proposed device can be used as a promising device for various small power applications. Further, this device not only provides improved DC and Analog/RF electrical parameters but also provides small footprint due to vertically aligned architecture.

Interface engineering of β-Ga2O3 MOS-type Schottky barrier diode using an ultrathin HfO2 interlayer

Low leakage current and high breakdown voltage are critically important to design high performance Schottky barrier diodes. In this work, a low leakage current was reported by studying the effect of inserting an ultrathin HfO2 layer using atomic-layer deposition with different cycle number at the interface between Ni and β-Ga2O3 for different annealing temperatures. A remarkable decrease in leakage current from 5.68 × 10−3 to 2.97 × 10−6 A/cm² at -300 V and a breakdown voltage increase from -467 to -556 V, were achieved when two cycles of HfO2 are inserted and annealed at 400°C. The leakage current decreases from 9.87 × 10−5 to 2.14 × 10−5 A/cm² for 200°C annealing temperature and from 1.035 × 10−4 to 2.56 × 10−6 A/cm² for as-deposited Metal-oxide semiconductor based Schottky barrier diode (MOSSBD) only after 2-cycles (∼2 Å) HfO2 is inserted. As the number of HfO2 cycles was increased (2–8 cycles) and the annealing temperature is varied, leakage current and breakdown voltage are affected. To investigate these variations in leakage current and breakdown voltage, Silvaco TCAD simulator is used. Good agreement is obtained between experiment and simulation by considering the fixed charge density in HfO2 (positive fixed charge density is related to oxygen vacancy density in HfO2 and the interfacial trap (reduced by annealing), and, where necessary, also considering the inhomogeneity of the Schottky barrier height to understand the main reason for the abrupt increase in leakage current at a specific reverse voltage.

Self‐Alignment Embedded Thin‐Film Transistor with High Transparency and Optimized Performance

AbstractAmorphous oxide semiconductor thin‐film transistors (AOS TFTs) have shown significant potential in the applications of increasingly advanced transparent and flexible electronic devices, where high speed, high transparency, and low power consumption are highly demanded. Yet, typical back‐channel etch (BCE) configuration used in the majority of TFTs still suffers from poor gate controllability, severe electrical field dispersion, relatively large parasitic capacitance and contact resistance. Here, a new embedded structure for TFTs with self‐alignment and even simpler fabrication process, outperforming conventional BCE counterpart in above aspects, is proposed in this work. More concentrated electrical field, improved gate control ability accompanied with lower contact resistance are achieved in the embedded TFTs. Consequently, superior electrical characteristics with subthreshold swing of 106.7 mV dec−1 and mobility as high as 32.10 cm2 V−1 s−1 are obtained. In addition, leakage current as well as contact resistance evidently decline compared to that in traditional BCE TFTs. By the assistance of Silvaco TCAD simulation, the performance and mechanism behind are cross‐validated from another perspective. Overall, such embedded configuration has equipped TFTs with appealing performance and it is also possible to enable other devices exploiting such structure with new possibility and thus a broader application.

Design of vertical diamond Schottky barrier diode with a novel beveled junction termination extension

In this paper, vertical diamond Schottky barrier diode with a beveled junction termination extension is designed by using Silvaco TCAD. We firstly investigate the effects of the pn junction termination extension on the electrical performances to optimize the doping concentration. In addition, the beveled structure with an angle of 45° decreases the current conduction path slightly, but it also enhances the reverse breakdown voltage effectively. By combining the junction termination extension and beveled structures, a new termination structure is proposed for the vertical diamond Schottky barrier diode. Under forward bias, the depletion region introduced by the pn junction hindrances the current conduction slightly and increases the on-resistance. However, the electric field crowding phenomenon is alleviated drastically under reverse bias, resulting in a more uniform electric field distribution and high breakdown voltage. Therefore, the beveled junction termination structure is promising to balance the on-resistance and the reverse breakdown voltage of the diamond Schottky barrier diode.

Investigation and Improvement of Switching Characteristics of SiC Optically Controlled Transistor

Aiming to the switching characteristics of SiC optically controlled transistor, SiC NPN optically controlled transistor was investigated through Silvaco TCAD. The results show that under 4500V bias voltage, the turn-on and turn-off dV/dt of the SiC transistor are 428.5V/ns and 23.9V/ns, respectively. And the tailing problem in the turn-off process is obvious. In order to improve the switching characteristics of SiC optically controlled transistor, the minority carrier lifetime in base layer is regional controlled. The simulation results indicate that, by using minority carrier lifetime control technology, the turn-off time and turn-off dV/dt are improved by about 28.2% and 39.3%, respectively. Meanwhile, turn-on time and turn-on dV/dt are only degenerated by about 3.6% and 3.4%, respectively. The overall level of switching characteristics of SiC optically controlled transistor are improved.

Investigation of the Self-Heating Effect in High Performance Organic TFTs With Multi-Finger Structure

This study investigated the impact of Joule heating under high current operation on multi-finger organic thin film transistors (OTFTs). The degradation was examined for a range of devices with different numbers of fingers (N = 4, 6, and 10). Due to the heat accumulation during operation, significant electrical degradation was observed at high currents. Under bias stress, with increasing number of fingers, the electrical characteristics exhibited different degrees of degradation, and an abnormal hump was observed in devices with 10 fingers. To examine the effect of self-heating, OTFTs were prepared on two substrates, polyimide and glass, and the causes of degradation were investigated at both room temperature and low temperatures. In addition, AC operation was proposed. Finally, a Silvaco TCAD simulation was made to model the device self-heating and illustrate the effect of the number of fingers on the bias stress.

Numerical Investigation of Perovskite and u-CIGS Based Tandem Solar Cells Using Silvaco TCAD Simulation

Numerical Investigation of Perovskite and u-CIGS Based Tandem Solar Cells Using Silvaco TCAD Simulation

Effect of uniaxial strain on characteristic frequency of scaled SiGe HBT with embedded stress raiser

In order to further improve the high-frequency characteristics of highly scaled SiGe HBT and consider the compatibility with the mature CMOS technology, a new SiGe HBT structure is proposed by introducing an embedded Si1−yGey stress raiser to produce additional uniaxial stress in the bulk collector region. The energy-band configuration of multi-layered emitter has been investigated by the estimation of the strain effect, and then the influence of stress raiser on the electrical properties and frequency response has been studied by employing the SILVACO TCAD tools. The results show that the device performance has been enhanced to different degrees by altering the Ge fraction (y) in the stress raiser. At y = 0.3, the current gain is increased by approximately 6% compared to the case without stress in the collector region (y = 0). For the case of a uniform Si0.75Ge0.25 base, the cut-off frequency (fT) and the maximum oscillating frequency (fmax) are, respectively, peaked at 507.7 GHz and 730.7 GHz. Approximately 29.1% improvement in fT and 71.5% improvement in fmax have been achieved for the proposed HBT device in comparison with an equivalent traditional SiGe HBT. At y = 0.1, the frequency characteristic is considered the best due to the maximum of fT × fmax product.

Analogue tuning of junction-less strained DG-MODFET

This paper discusses an extensive investigation on the influence of work-function (WF) tuning on analogue properties of the n-type junction-less strained double-gate MOSFET. The investigation on the device has been conducted with fixed level of input parameters operating in saturation mode by taking the dependency of analogue properties on the WF tuning into account. Numerical simulation was performed using industrial-based process/device simulator, Silvaco TCAD tools. The simulation results revealed that analogue properties of the device such as transconductance (gm), transconductance generation factor (TGF), output conductance (gd) and early voltage (VEA) exhibited an increase of ~17.4%, ~104.7%, 96% and 69.4% respectively as the WF is slightly minimized. However, the output impedance (ro), and intrinsic gain (AV) were deteriorated for ~58.4% and ~16.2% respectively as the WF is slightly minimized.

Performance Investigation of a Proposed Flipped npn Microstructure Silicon Solar Cell Using TCAD Simulation

This work aims at inspecting the device operation and performance of a novel flipped npn microstructure solar cell based on low-cost heavily doped silicon wafers. The flipped structure was designed to eliminate the shadowing effect as applied in the conventional silicon-based interdigitated back-contact cell (IBC). Due to the disappearance of the shadowing impact, the optical performance and short-circuit current density of the structure have been improved. Accordingly, the cell power conversion efficiency (PCE) has been improved in comparison to the conventional npn solar cell microstructure. A detailed analysis of the flipped npn structure was carried out in which we performed TCAD simulations for the electrical and optical performance of the flipped cell. Additionally, a comparison between the presented flipped microstructure and the conventional npn solar cell was accomplished. The PCE of the conventional npn structure was found to be 14.5%, while it was about 15% for the flipped structure when using the same cell physical parameters. Furthermore, the surface recombination velocity and base bulk lifetime, which are the most important recombination parameters, were studied to investigate their influence on the flipped microstructure performance. An efficiency of up to 16% could be reached when some design parameters were properly fine-tuned. Moreover, the impact of the different physical models on the performance of the proposed cell was studied, and it was revealed that band gap narrowing effect was the most significant factor limiting the open-circuit voltage. All the simulations accomplished in this analysis were carried out using the SILVACO TCAD process and device simulators.

A Fast Recovery Vertical Superjunction MOSFET with n-Si and p-3C-SiC Pillars

In the traditional SJ MOSFET structure, n/p pillars with the same doping concentrations in the drift region are introduced to decrease the on-resistance. However, SJ MOSFET will turn on the parasitic diodes due to fast reverse recovery, further inducing severe oscillation in the reverse recovery of the device and the corresponding adverse effect on the circuit. In this study, a fast recovery vertical superjunction (SJ) MOSFET with n-Si and p-3C-SiC pillars was studied. Unlike other structures, such as the 4H-SiC superjunction UMOSFET with a heterojunction diode or the ultra-low recovery charge cell-distributed Schottky contacts SJ-MOSFET with integrated isolated NMOS, we introduce a Schottky barrier diode (SBD) on the source contact at the top of the n-Si pillar in the SJ-MOSFET to improve the device reverse recovery. The simulation software TCAD Silvaco was utilized to simulate the device properties. Compared with the conventional Si SJ, the proposed Si/SiC SJ with the Schottky barrier diode (SBD) connected demonstrated a lower reverse recovery charge, which was reduced by 90.5%, respectively. The waveform of the reverse recovery current demonstrates that the electrons in the device are withdrawn from SBD during reverse recovery, preventing the opening of the parasitic diode in the SJ MOSFET. Finally, another structure is illustrated to decrease the gate capacitance by introducing a thin p-base layer between the gate metal and N-Si pillar so that it can improve the switching characteristics of devices. The open-loss and off-loss of the improved device were reduced by 33% and 42.3%, respectively.

Design and fabrication of graphene/CdS Schottky junction for photovoltaic solar cell applications

In this report, we study the optimal design and simulation of Schottky junction solar cells consisting of cadmium sulfide (CdS) and graphene layer using Silvaco TCAD Atlas software. During device modeling the thickness of the top layer of graphene as an electrode and the middle semiconducting layer of CdS as an active region is taken as 10 and 70 nm, respectively. Polyethylene terephthalate (PET) is used as the flexible substrate for the study. We also report the fabrication of flexible solar cells on PET substrates composed of CdS and graphene synthesized in-house by solution process. The I-V characteristics have been undertaken in both the simulated and fabricated devices with structure graphene/CdS/PET. Under AM 1.5 G, the fabricated device with the structure graphene/CdS/PET shows an open- circuit voltage (Voc) of 0.163 V, a short circuit current density (Jsc) of 0.00063 A/m2 and a fill factor (FF) of 56.50%. The Ideality factor and reverse saturation current of the device is determined to be 9.6 and 0.063 µA, respectively.

Simulation Study of Single-Event Effects for the 4H-SiC VDMOSFET With Ultralow On-Resistance

Silicon carbide (SiC) vertical-diffused metal oxide field transistor (VDMOSFET) is an important power device for aerospace application. However, it is sensitive to heavy particles radiation in space which can cause catastrophic single-event effects (SEEs). In this article, a method of SEE hardening at a high linear energy transfer (LET) value range is studied to the 1.2 kV-rated SiC VDMOSFET by the 2-D numerical simulator SILVACO TCAD. Simulation results illustrate that, compared with the VDMOSFET which only has four buffer (FB-VDMOSFET) layers, the improved MOSFET could increase the abilities of single-event burnout (SEB) and the single-event gate rupture (SEGR) of the device effectively. At the same time, the proposed MOSFET has the lower specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on, sp}}$ </tex-math></inline-formula> ) at room temperature. As a result, the gate oxide of the FB-VDMOSFET has reached 7.5 MV/cm and the maximum temperature reached 2480 K at a voltage of 600 V and an LET value of 0.5 pC/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> . However, the maximum temperature of the improved VDMOSFET is 2150 K when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathrm {DS}}$ </tex-math></inline-formula> = 950 V.

Reduction in RF Loss Based on AlGaN Back-Barrier Structure Changes.

We designed a high electron mobility transistor (HEMT) epitaxial structure based on an AlGaN/GaN heterojunction, utilizing Silvaco TCAD, and selected AlGaN with an aluminum composition of 0.1 as the back-barrier of the AlGaN/GaN heterojunction. We enhanced the confinement of the two-dimensional electron gas (2DEG) by optimizing the structural parameters of the back barrier, so that the leakage current of the buffer layer is reduced. Through these optimization methods, a lower drain leakage current and a good radio frequency performance were obtained. The device has a cut-off frequency of 48.9 GHz, a maximum oscillation frequency of 73.20 GHz, and a radio frequency loss of 0.239 dB/mm (at 6 GHz). This work provides a basis for the preparation of radio frequency devices with excellent frequency characteristics and low RF loss.

A new normalized direct conductance method for observation of Poole-Frenkel current

This article presents a method to distinguish between the various conduction mechanisms through insulators in MOS structures whose expressions are exponential functions of voltage. This method accounts for the voltage drop (ΔV) across the parasitic resistance that could be significantly present in series with the MOS structure. This graphical method is based on a new Normalized Direct Conductance function to extract the value ΔV. The validity of the proposed method has been ascertained by using Silvaco TCAD simulations and measurements of the gate leakage current of an experimental n-channel MOSFET. The band diagram with the corresponding numerical values also verifies the extracted value of ΔV. It is concluded that the dominant conduction mechanism is Poole-Frenkel for the middle gate voltage region while Hot Electron Injection dominates for low- and high-voltage regions.

Effect of temperature on analog/RF and linearity performance of InSb/Si heterojunction SOI TFET

This work reports the effect of temperature on analog/RF and linearity metrics of pocket doped InSb/Si heterojunction SOI TFET using Silvaco TCAD. In the proposed structure, the conventional SiO2 is replaced with SiO2/HfO2 that suppresses the ambipolar behavior and the n+ pocket introduced towards drain mitigates the effect of field induced quantum confinement which helps to enhance the drain current. The result obtained through simulation shows a better ION/IOFF and average subthreshold swing of 1011 to 107 and 29.3 to 38.5 when temperature varies in the range of 300–400 K. Analog/RF and linearity distortion performance at 400 K have been analyzed in terms of total capacitance, transconductance (2.4 ms/μm), transconductance frequency product (18.62 GHz/V), cutoff frequency (∼600 GHz), gain bandwidth product (5.3THZ), transit time (0.263 ps) and 1dB compression point (-6.6 dB). Reliability analysis shows a significant change in second harmonics with temperature which is unfavorable for subthreshold swing, ambipolar current, and ION/IOFF ratio.

A Snapback-Free and Low Turn-Off Loss 15 kV 4H–SiC IGBT with Multifunctional P-Floating Layer

In this paper, a 4H–SiC IGBT with a multifunctional P-floating layer (MP-IGBT) is proposed and investigated by Silvaco TCAD simulations. Compared with the conventional 4H–SiC field stop IGBT (FS-IGBT), the MP-IGBT structure features a P-floating layer structure under the N-buffer layer. The P-floating layer increases the distributed path resistance below the buffer layer to eliminate the snapback phenomenon. In addition, the P-floating layer acts as an amplifying stage for the hole currents’ injection. The snapback-free structure features a half-cell pitch of 10 μm. For the same forward voltage drop, the turn-off loss of the MP-IGBT structure is reduced by 42%.

22.8% efficient ion implanted PERC solar cell with a roadmap to achieve 23.5% efficiency: A process and device simulation study

Among all available photovoltaic (PV) technology options, c-Si based passivated emitter rear cell (PERC) has already proved its mettle by delivering more than 22% conversion efficiency at the industrial level. However, designing of PERC solar cell device remains a challenge owing to recombination and absorption losses, which eventually restrict the performance of the device toward achieving an Auger efficiency limit of 29.4%. The primary contributor to these losses is emitter recombination losses that limits the performance of PERC devices. The n+-emitter region in the proposed PERC devices is formed using ion implantation followed by a diffusion process. The impact of process variables such as dose (cm−2), energy (keV), diffusion time (s), and diffusion temperature (oC) on the PERC device performance is not much explored. Therefore, in an attempt to fulfill this research gap, the emitter region performance in terms of ion implantation of phosphorus, influence of local back surface field (BSF) doping concentration (1017 to 1019 cm−3), and back surface recombination velocity (SRV 101–107 cm/s) on PERC device performance followed by the loss analysis is examined in this work. An upright pyramid textured structure with constant height (5 μm) and industrial standard stacked dielectric anti-reflective coating layers, SiNX/SiO2 and Al2O3/SiNX at front and back side respectively is realized using different process statements such as deposit, etch, implantation, and diffusion with the help of a Silvaco TCAD software. Investigations reveal that the PERC device can deliver an efficiency of 22.8% with 150 μm boron-doped crystalline silicon (c-Si) wafer at an optimum phosphorous dose (5 × 1015 cm−2), BSF doping (1019 cm−3), and SRVn (107 cm/s). Short-circuit current density (JSC) of 40.8 mA/cm2, open-circuit voltage (VOC) of 0.686 V, and fill factor (FF) of 81.54% are obtained for the structure under consideration. A roadmap to achieve 23.5% conversion efficiency has also been reported by assuming a carrier selective contact at the backside with a surface recombination velocity of 10 cm/s.

Optimization AlGaN/GaN HEMT with Field Plate Structures.

AlGaN/GaN HEMTs with several different designs of field plate structure are studied for device optimization purposes. To increase device breakdown voltage, optimal dimensions of field plates were first investigated using Silvaco TCAD software, and the electrical characteristics of the devices are analyzed. Several devices were designed and fabricated based on the simulation results. It has been confirmed that the gate-source composite field plate (SG-FP) has a higher breakdown voltage than other types of field plate structures, with FOM reaches 504 MW/cm−2, showing that the device with SG-FP structure outperforms the other three structures. The experiment and simulation verify that the gate-source composite field plate optimizes FOM by increasing the breakdown voltage and reducing the intrinsic on-resistance so that the device has better electrical performance and a wider application range.

Analogue properties of junction-less strained dg-mosfet

This paper discusses an extensive investigation on the influence of work-function (WF) tuning on analogue properties of the n-type junction-less strained double-gate MOSFET. The investigation on the device has been conducted with fixed level of input parameters operating in saturation mode by taking the dependency of analogue properties on the WF tuning into account. Numerical simulation was performed using industrial-based process/device simulator, Silvaco TCAD tools. The simulation results revealed that analogue properties of the device such as transconductance (gm), transconductance generation factor (TGF), output conductance (gd) and early voltage (VEA) exhibited an increase of ~17.4%, ~104.7%, 96% and 69.4% respectively as the WF is slightly minimized. However, the output impedance (ro), and intrinsic gain (AV) were deteriorated for ~58.4% and ~16.2% respectively as the WF is slightly minimized.