GeSn based heterojunction double-gate tripple metal layer vertical TFET with enhanced DC and Analog/RF performance

Abstract

In this article, low-bandgap material GeSn and high bandgap Si material heterojunction (GeSn/Si) based double gate triple metal layer Vertical TFET is designed and analyzed by ATLAS Silvaco TCAD simulation tool. Higher ON-state current is obtained by this device owing to (i) the usage of novel low band-gap material i.e., GeSn and (ii) Vertical tunneling as the gate overlaps the source region. The incorporation of GeSn material not only enhances the ON-state current but also improves the SS, albeit trading off the OFF-state current and ambipolar current of the device. To control the ambipolar current and OFF-state current, variation in the gate to drain overlap and auxiliary gate metal work function has been done. The impact of the gate to drain overlap and auxiliary gate workfunction variation has been studied for various electrical parameters. Further through extensive simulation analysis, optimized dimensions have been obtained. An enormously high ION/IOFF ratio of the order of 1.6 × 1012, steepest point, and average subthreshold swing of 7.5 mV/dec and 12.3 mV/dec respectively has been achieved through this proposed device. In addition to this, comparison of the proposed device with other novel TFET devices reported in literature has been done. From the comparison, it has been concluded that better results are obtained by the proposed device in terms of ION, IAMB, ION/IOFF ratio, SSavg, and gm. Therefore, this novel proposed device can be used as a promising device for various small power applications. Further, this device not only provides improved DC and Analog/RF electrical parameters but also provides small footprint due to vertically aligned architecture.