Silicon Vias Research Articles

Bottom-up Gold Filling of High Aspect Ratio Trenches :Toward a Mechanistic Understanding

Cu is the standard choice for the formation of multi-level 3-D interconnects allowing for microelectronic chip-stacking (1). This is predicated on the well-defined additive chemistries that drive the superconformal Cu filling of through silicon vias (TSVs) and trenches (2). To transition to Au filling of complex 3-D Si architectures for optoelectronic applications, analogous chemistries that enable preferential filling within recessed silicon features must be developed. To date the state of the art for void free Au filling has come from the use of a Pb additive in both KAu(CN)2 (3, 4) and Na3Au(SO3)2 (5) electrolytes. Both of these systems yield superconformal filling via a curvature enhanced accelerator coverage (CEAC) mechanism. However, due to the toxicity of CN- and Pb2+ containing electrolytes, alternatives must be explored. Recently, it has been demonstrated that the addition of Bi to alkaline Na3Au(SO3)2 electrolytes yields preferential bottom-up Au electrodeposition in Si trenches, with limited deposition on the free surface (6). The addition of Bi to the intrinsically suppressed Na3Au(SO3)2 electrolyte clearly accelerates deposition(6, 7). However, growth in this system does not propagate via the typical CEAC mechanism demonstrated in other accelerated systems (3). Instead the growth propagates via a mechanism more closely resembling that of S-shaped negative differential resistance (S-NDR) based on suppression breakdown, typical for suppressor based additive systems(8). This talk will explore the utilization of this Bi, Na3Au(SO3)2 electrolyte system for the bottom-up filling of high aspect ratio silicon trenches. The effect of; potential, additive concentration and electrolyte transport will be explored on the filling of features with aspect ratios ranging from 1.5 to 17. Additionally, the chemical and morphological nature of the accelerated bottoms of features, and of the passive free surface, will be compared via x-ray photoelectron spectroscopy, scanning electron microscopy and anodic stripping voltammetry to gain mechanistic insight into the role of Bi in deposition acceleration and feature localization. P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans and H. Deligianni, IBM J. Res. Dev., 42, 567 (1998).T. P. Moffat, D. Wheeler, M. D. Edelstein and D. Josell, IBM J. Res. Dev., 49, 19 (2005).D. Josell, C. R. Beauchamp, D. R. Kelley, C. A. Witt and T. P. Moffat, Electrochem. Solid-State Lett., 8, C54 (2005).D. Josell, D. Wheeler and T. P. Moffat, J. Electrochem. Soc., 153, C11 (2006).D. Josell and T. P. Moffat, J. Electrochem. Soc., 160, D3009 (2013).D. Josell and T. P. Moffat, J. Electrochem. Soc., 166, D3022 (2019).I. D. E. McIntyre and W. F. Peck, J. Electrochem. Soc., 123, 1800 (1976).S.-K. Kim, J. E. Bonevich, D. Josell and T. P. Moffat, J. Electrochem. Soc., 154, D443 (2007).

Void-Free Copper Electrodeposition in Full Wafer Thickness through-Silicon Vias with 10:1 Aspect Ratios

The incorporation of copper-filled, mesoscale through-silicon-vias (TSVs) as a three-dimensional integration technique allows for increased input/output per unit volume compared to wire bonded microelectronic devices. Mesoscale TSVs that span the full thickness of a silicon wafer allow for preservation of a large radius of curvature during multi-layer device fabrication and for conservation of mass in the device, which is often a requirement in MEMS applications. The damascene process is commonly implemented for Cu electrodeposition in high aspect ratio features and typically involves a three-additive system in a CuSO4-H2SO4 electrolyte. However, a single-additive system has recently been shown capable of achieving bottom-up superfilling in features with higher aspect ratios than those commonly used in damascene interconnects.[i] This resistive electrodeposition system utilizes CuSO4, methane sulfonic acid (MSA), chloride, and a poloxamine suppressor additive. Cyclic voltammetry (CV) can be used to characterize the plating solution and identify a potential range that exhibits hysteresis in the voltage-current relationship that is caused by suppressor disruption at the cathode surface during electrodeposition. This hysteretic region serves as an operating window where void-free Cu filling of high aspect ratio features may be achieved. Using this chemistry, potentiostatic and galvanostatic plating conditions for void-free filling were developed for 100 μm diameter vias that are 600 μm deep, a 6:1 aspect ratio.[ii],[iii] Cu electrodeposition in TSVs with a higher aspect ratio of 10:1 is currently under investigation. These TSVs have a 62.5 μm diameter etched into a 625 μm thick silicon-on-insulator (SOI) wafer. Conditions that produce void free, bottom-up filling for 100 μm diameter TSVs have not directly translated to fill 62.5 μm diameter TSVs. In this work, the poloxamine suppressor concentration, current, potential, and sample rotation rate were varied to analyze their effect on the fill profile in these 62.5 μm diameter TSVs. Fill profiles were analyzed after mechanically cross-sectioning and optically imaging the samples. Cu fill profiles were also obtained through X-ray computed tomography (CT) scans. This work details the experimental approach associated with determining galvanostatic and potentiostatic plating conditions for 62.5 μm diameter TSVs and presents the resultant fill profiles of Cu in these vias. Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. [i]. Moffat, T. P., and D. Josell. "Extreme bottom-up superfilling of through-silicon-vias by damascene processing: suppressor disruption, positive feedback and turing patterns." Journal of the Electrochemical Society 159.4 (2012): D208-D216. [ii]. Menk, L. A. et. al. “Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology.” Journal of the Electrochemical Society 166.1 (2019): D3066-D3071. [iii]. Menk, L. A. et. al. “Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs” Journal of the Electrochemical Society 166.1 (2019).

Fast 3D Integrated Circuit Placement Methodology using Merging Technique

In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.

A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs

Since the physical defects such as resistive open and leakage in through silicon vias (TSVs) caused by immature manufacturing techniques tend to undermine the reliability and yield of 3-D integrated circuits, it is very important to test the TSV as early as possible in the fabrication process. There are some shortcomings in the existing prebond TSV test techniques, such as incomprehensive fault coverage, large area overhead, and additional test time. To overcome these problems, a noninvasive solution for prebond TSV test based on pulse shrinking is proposed in this paper. This method makes use of the fact that defects in TSV lead to variation in the propagation delay—the rise and fall times are first transformed into pulse width, and the pulse shrinking technique is used to digitize the pulse width into a digital code which is then compared with an expected value for a fault-free TSV. Experiments on defect detection are carried out using HSPICE simulations with realistic models for 45-nm CMOS technology. The results show that the proposed method performs better than the existing methods in terms of fault coverage, area overhead, and test time.

An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors

Uncore components such as cache hierarchy and on-chip interconnects consume a significant portion of overall energy consumption in emerging embedded processors. In Nanoscale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM-based on-chip cache memories and interconnections. To address this issue, non-volatile memory technologies such as STT-RAMs have been proposed as a replacement for SRAM cells due to their near-zero static power and high memory density. Nonetheless, STT-RAMs suffer from some failures such as read-disturb and limited endurance as well as high switching energy. One effective way to decrease the STTRAMs’ switching energy is to reduce their retention time; however, reducing the retention time has a negative impact on the reliability of STT-RAM cells. In this paper, we propose a heterogeneous last level cache (LLC) architecture for 3D embedded chip-multiprocessors (3D eCMPs) which employs two types of STT-RAM memory banks with retention time of 1s and 10ms to provide a beneficial trade-off between reliability, energy consumption, and performance. To this end, we also propose a convex optimization model to find the optimal configurations for these two kinds of memory banks. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias (TSVs) as a main component of on-chip interconnection for building 3D CMPs is another important target of the proposed optimization approach. Experimental results show that the proposed method improves the energy-delay products and throughput by about 69% and 34.5% on average compared with SRAM configurations.

Effects of twin boundaries on the void formation in Cu-filled through silicon vias under thermal process

We reported on the study of the thermal mechanical reliability of Cu-filled through silicon via (TSV) under 450 °C thermal loading. It was found that the voids could be generated at twin boundaries in TSV-Cu after thermal process. To study the mechanism of void formation at twin boundaries, the voided regions were characterized by focused ion beam—scanning electron microscope (FIB-SEM), the crystallographic orientation of Cu grains and the microstructure of twin boundaries was analyzed by means of electron backscattered diffraction (EBSD) and transmission electron microscope (TEM). Stress induced voids were considered to be generated at twin boundaries because of the stress concentration induced by three possible factors: crystallographic orientation differences of Cu grains near the twin boundary, interface decohesion of twin boundary and morphology of twin boundary.

Improved transmission line model for high-frequency modelling of through silicon vias

ABSTRACTAccurate and reliable models can support Through Silicon Via (TSV) testing methods and improve the quality of 3D ICs. A model for expressing resistance and inductance of TSVs at frequencies up to 50 GHz is proposed. It is based on the two-parallel transmission cylindrical wires model, known also as the Transmission Line Model and improved through the fitting to ANSYS Q3D simulation results. The proximity effect between neighbouring TSVs that alters the paths through which current flows is empowered at high frequencies. The consideration of the dependence of the proximity effect on frequency for calculating TSV resistance and inductance is the main contribution of this work. Additionally, the modelling of resistance is extended to accurately correspond to a TSV in an array. The proposed models are in good agreement with the simulator results with an average error below 2% and 5.4% for the resistance and the inductance, respectively. The maximum error is 3% and 9.1%, respectively. In the case of the resistance of a TSV in an array, the maximum error is 4.7%. As long as the coefficients of the proposed equations have been extracted, the time for resistance and inductance calculation based on the presented models is negligible, compared to the time-consuming EM simulation.

Thermal management of the through silicon vias in 3-D integrated circuits

The through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit integration. However, its size and the property of the filled-materials are two factors affecting the thermal behavior of the integrated circuits. In this paper, we design 3-D integrated circuits with different through silicon via models and analyze the effect of different material-filled through silicon vias, aspect ratio and thermal conductivity of the dielectric on the steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for through silicon vias in 3-D integrated circuits.

Effect of Chloride Concentration on Copper Deposition in Through Silicon Vias

Bottom-up Cu deposition in metallized through silicon vias (TSV) depends on a co-adsorbed polyether–Cl− suppressor layer that selectively breaks down within recessed surface features. This work explores Cu deposition when formation of the suppressor blocking layer is limited by the flux of Cl−. This constraint leads to a transition from passive surfaces to active deposition partway down the via sidewall due to coupling between suppressor formation and breakdown as well as surface topography. The impact of Cl− concentration and hydrodynamics on the formation of the suppressor surface phase and its potential-dependent breakdown is examined. The onset of suppression breakdown is related to the local Cl− coverage as determined by the adsorption isotherm or transport limited flux. A two-additive co-adsorption model is presented that correlates the voltammetric potential of suppression breakdown with the depth of the passive-active transition during TSV filling under conditions of transport limited flux and incorporation of Cl−. The utility of potential waveforms to optimize the feature filling process is demonstrated. At higher Cl− concentrations (≥80 μmol/L), sidewall breakdown during Cu deposition occurs near the bottom of the via followed by a shift to bottom-up growth like that seen at higher Cl− concentrations.

V-Band End-Fire Radiating Planar Micromachined Helical Antenna Using Through-Glass Silicon Via (TGSV) Technology

In this paper, we demonstrate a V-band planar micromachined helical antenna (PHA) with end-fire radiation on the glass substrate. The planar rectangular helical configuration is realized using the novel through-glass silicon via (TGSV) technology. The proposed micromachined antenna is designed and fabricated on a borosilicate glass substrate of thickness 350 μm, which has a very low-dielectric loss compared to silicon at millimeter-wave bands. The proposed PHA is fed by a microstrip line, and the planar helical configuration with 3.25 turns with a truncated ground plane is designed for achieving wideband end-fire radiation with seven tungsten-coated silicon vias and six connected gold arm patterns, which are fabricated using the TGSV technology. The electrical length of the proposed antenna is (3 λ o ×1.4 λ o ). The designed antenna operates at the center frequency of 58 GHz. A prototype of the proposed antenna is fabricated by micromachining technology and tested. The simulated and measured results show that the proposed antenna has a wide operational bandwidth of 50.3 to 65 GHz for |S 11 | <; -10 dB with a fractional bandwidth (FBW) of 25.5%. The measured peak gain is 6.3 dBi, and measured efficiency is 62% at the center frequency of 58 GHz. All measurements are in close agreement with simulated results. The proposed planar helical antenna with end-fire radiation is useful for applications in traveling-wave-tubes operating in millimeter-wave and higher frequencies, millimeter-wave on-board wireless communication, radar imaging, and tracking applications.

Research on a 3D Encapsulation Technique for Capacitive MEMS Sensors Based on Through Silicon Via.

A novel three-dimensional (3D) hermetic packaging technique suitable for capacitive microelectromechanical systems (MEMS) sensors is studied. The composite substrate with through silicon via (TSV) is used as the encapsulation cap fabricated by a glass-in-silicon (GIS) reflow process. In particular, the low-resistivity silicon pillars embedded in the glass cap are designed to serve as the electrical feedthrough and the fixed capacitance plate at the same time to simplify the fabrication process and improve the reliability. The fabrication process and the properties of the encapsulation cap were studied systematically. The resistance of the silicon vertical feedthrough was measured to be as low as 263.5 mΩ, indicating a good electrical interconnection property. Furthermore, the surface root-mean-square (RMS) roughnesses of glass and silicon were measured to be 1.12 nm and 0.814 nm, respectively, which were small enough for the final wafer bonding process. Anodic bonding between the encapsulation cap and the silicon wafer with sensing structures was conducted in a vacuum to complete the hermetic encapsulation. The proposed packaging scheme was successfully applied to a capacitive gyroscope. The quality factor of the packaged gyroscope achieved above 220,000, which was at least one order of magnitude larger than that of the unpackaged. The validity of the proposed packaging scheme could be verified. Furthermore, the packaging failure was less than 1%, which demonstrated the feasibility and reliability of the technique for high-performance MEMS vacuum packaging.

Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs

A methanesulfonic acid (MSA) electrolyte with a single suppressor additive was used for potentiostatic bottom-up filling of copper in mesoscale through silicon vias (TSVs). Conversly, galvanostatic deposition is desirable for production level full wafer plating tools as they are typically not equipped with reference electrodes which are required for potentiostatic plating. Potentiostatic deposition was used to determine the over-potential required for bottom-up TSV filling and the resultant current was measured to establish a range of current densities to investigate for galvanostatic deposition. Galvanostatic plating conditions were then optimized to achieve void-free bottom-up filling in mesoscale TSVs for a range of sample sizes.

Notice of Retraction: Defects Identification in a TSV Daisy-Chain Structure by a Machine Learning Approach

This work applies the paradigm of the machine learning to the identification of type and position of short-and open-circuit defects along a three-dimensional daisy-chain signal channel in presence of through silicon vias. A suitable artificial neural network is designed, trained, and used for this task. This contribution discusses the advantages and limitations of this approach quantifying the differences among the real and estimated positions of the defects.

3D system integration on 300 mm wafer level: High-aspect-ratio TSVs with ruthenium seed layer by thermal ALD and subsequent copper electroplating

The copper electrochemical deposition (Cu-ECD) filling capability of high aspect ratio through silicon vias (HAR-TSVs) and homogeneity over 300 mm wafers were investigated on a film stack of thermal ALD (thALD) TaxNy barrier with thermal ALD Ru seed in comparison to TixNy barrier with a standard Cu i-PVD seed layer using a commercial 300 mm plating tool. As a first step, Cu-ECD was conducted on wafers with TSV blind holes with aspect ratios (AR) of 10 to 12. To achieve this, a thermal ALD film stack of approximately 6 nm TaxNy and 9 nm Ru (with a sheet resistance of [25.6 ± 1.4] Ω/ϒ) were deposited at 250 °C. The reactants for the barrier layer were (tert-butylimido)tris(diethylamino)tantalum(V) (TBTDET) and ammonia (NH3) as co-reactant. For the Ru seed layer deposition (ethylcyclopentadienyl)(pyrrolyl)ruthenium(II) (ECPR) and molecular oxygen as co-reactant were used supplemented by a hydrogen purge step after every third ALD cycle. The corresponding ALD growth was observed during the entire process by in-situ real-time spectroscopic ellipsometry (irtSE). Blister-free deposition and satisfactory film stack adhesion with no delamination was verified ex situ by scanning electron microscopy (SEM). The deposited copper inside the TSVs was analyzed by focused ion beam (FIB) imaging and X-ray tomography.The Cu ECD filling capability in HAR-TSVs was shown on a film stack of thALD TaxNy thALD Ru seed using a commercial industry standard 300 mm plating tool. A novel blister-free ultra-thin Ru ALD film having good adhesion properties and unique advantages, e. g. high conformity in high-aspect-ratio through-silicon vias large-scale film uniformity over 300 mm wafers, as well as good reproducibility was developed.

Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology

An electrodeposition process for void-free bottom-up filling of sub-millimeter scale through silicon vias (TSVs) with Cu is detailed. The 600 μm deep and nominally 125 μm diameter metallized vias were filled with Cu in less than 7 hours under potentiostatic control. The electrolyte is comprised of 1.25 mol/L CuSO4 – 0.25 mol/L CH3SO3H with polyether and halide additions that selectively suppress metal deposition on the free surface and side walls. A brief qualitative discussion of the procedures used to identify and optimize the bottom-up void-free feature filling is presented.

A Hybrid Non-destructive Measuring Method of Three-dimensional Profile of Through Silicon Vias for Realization of Smart Devices

Smart devices have been fabricated based on design concept of multiple layer structures which require through silicon vias to transfer electric signals between stacked layers. Because even a single defect leads to fail of the packaged devices, the dimensions of the through silicon vias are needed to be measured through whole sampling inspection process. For that, a novel hybrid optical probe working based on optical interferometry, confocal microscopy and optical microscopy was proposed and realized for enhancing inspection efficiency in this report. The optical microscope was utilized for coarsely monitoring the specimen in a large field of view, and the other methods of interferometry and confocal microscopy were used to measure dimensions of small features with high speed by eliminating time-consuming process of the vertical scanning. Owing to the importance of the reliability, the uncertainty evaluation of the proposed method was fulfilled, which offers a practical example for estimating the performance of inspection machines operating with numerous principles at semiconductor manufacturing sites. According to the measurement results, the mean values of the diameter and depth were 40.420 µm and 5.954 µm with the expanded uncertainty of 0.050 µm (k = 2) and 0.208 µm (k = 2), respectively.

Study of Three-Dimensional Small Chip Stacking Using Low Cost Wafer-Level Micro-bump/B-Stage Adhesive Film Hybrid Bonding and Via-Last TSVs

Three-dimensional (3-D) small chip stacking using low cost wafer-level insert-bump hybrid bonding and via-last TSVs is proposed and investigated. The proposed hybrid bonding method realized by micro Cu pillar solder bumps and photo-patternable B-stage adhesive film has been successfully applied to an 8 inch wafer with 86 255 gross dies and a bump pitch of 150 μm. The complete process flow is successfully validated and a well electrical connectivity for the whole wafer is obtained. Two hybrid bonding approaches, i.e., “adhesive-first” hybrid bonding and “Cu pillar bump-first” hybrid bonding, are studied. A void-free hybrid bonding interface with a final gap between top chip and bottom chip lower than 30 μm is achieved using the “Cu pillar bump-first” hybrid bonding approach. The interaction of SnAg solder with electroless Ni-P/immersion Au and electro Ni are investigated. Two types of interfacial compounds, i.e., Ni3Sn4 and P-rich Ni layer containing Sn atoms, are found. The via-last through silicon vias (TSVs) have a diameter of 40 μm and a depth of 95 μm. The results indicate that it is a promising method for 3-D integrated circuits stacking technology using hybrid bonding and via-last TSVs.

Highlighting two integration technologies based on vias: Through silicon vias and embedded components into PCB. Strengths and weaknesses for manufacturing and reliability

Manufacturers of electronic components and systems are currently undergoing profound changes. For foundry manufacturers, Moore's law is fast approaching, and they must find technological solutions to further densify their electronic circuits. For PCB (Printed Circuit Board) manufacturers, the change is even more important as they have to bury components inside their circuitry. In this paper we present physics analysis and simulations of copper via to study the impact of this kind of assembly process on the reliability of these new electronic circuits. Manufacturers can head towards the through silicon (TSV) via or embedded components. First, we present analysis made with the SAM (scanning acoustic microscope) using shear wave's generation to extract information about strain induced by the copper via in TSV. Finite element analysis shows the correlation between the two technologies. Secondly, we present finite element analysis made on embedded active components inside PCB and an evaluation of the fatigue lifetime on via. TDM (Topography and Deformation Measurements) are made to calibrate the model generated by finite elements. A discussion is then conducted to determine the weaknesses and strengths of each of these technologies in order to determine their long-term robustness.

A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic 3-D IC

An advanced neurophysiological computing system can incorporate a 3-D integration system composed of emerging nano-scale devices to provide massive parallelism having high speed, low cost, and energy efficient hardware implementation. Due to process technology constraints, a certain amount of redundant through silicon vias (TSVs) and dummy TSVs are always required in a 3-D integrated system. In this paper, we propose to use these redundant and dummy TSVs to supply the neuronal membrane capacitance that maps the membrane electrical activity in a hybrid 3-D neuromorphic system. This proposition could also serve the need of neuronal ion transportation dynamics. We also investigate two new methodologies that could significantly enhance the TSV capacitance in a 3-D neuromorphic system. The capacitance of these enhanced TSVs is studied with analytical models; the accuracy of the models are evaluated against 3-D field extracted values. The advantage of using the TSVs to mimic membrane capacitance in a 3-D neuromorphic chip is demonstrated through comparisons of both silicon area and energy consumption against their 2-D counterpart designs.

Energy-aware partitioning of fault-tolerant irregular topologies for 3D network-on-chips

Irregular topologies have become more attractive choice than their regular counterparts for network-on-chip (NoC) designs since they have lower power consumptions, higher throughputs, and lower latencies. These topologies use the minimum required network resources to minimize some design objectives such as energy and performance. Hence, they are designed to guarantee only one way between application nodes. Therefore, a single permanent link failure may cause a complete breakdown for the designed chip. Previous studies presented an irregular topology design method that adds extra routers and links to have alternative paths between nodes. These topologies use the main routing table if there is no failure on the design. It stores the alternative routing options on routing tables, which can be activated by the external pins of the chip when there is a fault on a link. However, the alternative routings increase the energy consumption and latency of the packets. One solution to mitigate the energy and latency increase can be implementing the design as a 3D NoC, which utilizes faster and less energy consuming through silicon vias between different layers. In this study, we present a method that generates irregular fault-tolerant topology and routing for 3D NoCs. We compare the proposed method with its 2D counterpart on three benchmarks from literature based on energy consumption and chip area. The results show that 3D-based method brings significant energy improvements, especially in alternative routings. Additionally, we observed that employing 3D structure reduces the area proportional to the number of 3D layers, which makes the 3D design a perfect choice for the designed fault-tolerant system.