An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors

Abstract

Uncore components such as cache hierarchy and on-chip interconnects consume a significant portion of overall energy consumption in emerging embedded processors. In Nanoscale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM-based on-chip cache memories and interconnections. To address this issue, non-volatile memory technologies such as STT-RAMs have been proposed as a replacement for SRAM cells due to their near-zero static power and high memory density. Nonetheless, STT-RAMs suffer from some failures such as read-disturb and limited endurance as well as high switching energy. One effective way to decrease the STTRAMs’ switching energy is to reduce their retention time; however, reducing the retention time has a negative impact on the reliability of STT-RAM cells. In this paper, we propose a heterogeneous last level cache (LLC) architecture for 3D embedded chip-multiprocessors (3D eCMPs) which employs two types of STT-RAM memory banks with retention time of 1s and 10ms to provide a beneficial trade-off between reliability, energy consumption, and performance. To this end, we also propose a convex optimization model to find the optimal configurations for these two kinds of memory banks. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias (TSVs) as a main component of on-chip interconnection for building 3D CMPs is another important target of the proposed optimization approach. Experimental results show that the proposed method improves the energy-delay products and throughput by about 69% and 34.5% on average compared with SRAM configurations.