Energy-aware partitioning of fault-tolerant irregular topologies for 3D network-on-chips

Abstract

Irregular topologies have become more attractive choice than their regular counterparts for network-on-chip (NoC) designs since they have lower power consumptions, higher throughputs, and lower latencies. These topologies use the minimum required network resources to minimize some design objectives such as energy and performance. Hence, they are designed to guarantee only one way between application nodes. Therefore, a single permanent link failure may cause a complete breakdown for the designed chip. Previous studies presented an irregular topology design method that adds extra routers and links to have alternative paths between nodes. These topologies use the main routing table if there is no failure on the design. It stores the alternative routing options on routing tables, which can be activated by the external pins of the chip when there is a fault on a link. However, the alternative routings increase the energy consumption and latency of the packets. One solution to mitigate the energy and latency increase can be implementing the design as a 3D NoC, which utilizes faster and less energy consuming through silicon vias between different layers. In this study, we present a method that generates irregular fault-tolerant topology and routing for 3D NoCs. We compare the proposed method with its 2D counterpart on three benchmarks from literature based on energy consumption and chip area. The results show that 3D-based method brings significant energy improvements, especially in alternative routings. Additionally, we observed that employing 3D structure reduces the area proportional to the number of 3D layers, which makes the 3D design a perfect choice for the designed fault-tolerant system.