Silicon-on-insulator Transistors Research Articles

Design study and spectroscopic performance of SOI pixel detector with a pinned depleted diode structure for X-ray astronomy

We have been developing silicon-on-insulator (SOI) pixel detectors with a pinned depleted diode (PDD) structure, named “XRPIX”, for X-ray astronomy. The PDD structure is formed in a thick p-type substrate, to which high negative voltage is applied to make it fully depleted. A pinned p-well is introduced at the backside of the insulator layer to reduce a dark current generation at the Si-SiO2 interface and to fix the back-gate voltage of the SOI transistors. An n-well is further introduced between the p-well and the substrate to make a potential barrier between them and suppress a leakage current. An optimization study on the n-well dopant concentration is necessary because a higher dopant concentration could result in a higher potential barrier but also in a larger sense-node capacitance leading to a lower spectroscopic performance, and vice versa. Based on a device simulation, we fabricated five candidate chips having different n-well dopant concentrations. We successfully found out the best n-well design, which suppressed a large leakage current and showed satisfactory X-ray spectroscopic performance. Too low and too high n-well dopant concentration chips showed a large leakage current and degraded X-ray spectroscopic performance, respectively. We also found that the dependency of X-ray spectroscopic performance on the n-well dopant concentration can be largely explained by the difference in sense-node capacitance.

Influence of Hot Carrier Degradation on the Characteristics of a High-Voltage SOI Transistor with a Large Drift Region

The results of studying the effect of hot carrier degradation on the electrical characteristics of high-power laterally diffused metal oxide semiconductor (LDMOS) transistors made according to the silicon-on-insulator (SOI) technology, with a long drift region with topological norms of 0.5 microns, are discussed. The analysis of the degradation of hot carriers in high electric fields is based on the experimental results and the additional use of an analytical model. The physical origin of this mechanism is related to the formation of traps at the Si/SiO2 interface. With the help of numerical analysis and experiments, the electrical character-istics of SOI nLDMOS transistors are considered in a wide range of control voltages in order to study their effect on the safe operation zone and reliability of the device under conditions of the degradation of hot carriers. The results of these studies allow us to conclude that a 20% expansion of the safe operation zone is possible.

Temperature-dependent thermal phonon relaxation time and its influence on ballistic-diffusive heat transport in SOI transistor

A simple model of the average thermal phonon relaxation time including its temperature dependency for silicon (Si) is proposed and incorporated with the gray version of the phonon Boltzmann transport equation to investigate its effect on the temperature distribution of the Si-layer in a silicon-on-insulator (SOI) transistor with heat generation (qv). Our analysis showed that the peak temperatures both in the nonlocal heating region and at the Si/SiO2 interface increase quadratically with increasing values of qv, while in the case of the temperature-independent, however, they show a linear increase with increasing qv. The results from this work will help in understanding the phonon transport at the device-level based on Si and will provide a way how to do an efficient thermal analysis of the device-level including all the frequency and temperature dependencies of the phonon transport properties.

Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits

Performances of high-frequency integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future lower power wireless communication systems operating in the millimeter-wave range. The high frequency performances of FD SOI transistors are presented at room but also at cryogenic and high temperature. Recently published results for FD SOI switches and low noise amplifiers are summarized. And finally, the potential interest and challenges to move from standard to high resistivity FD SOI substrates are discussed.

A critical evaluation based on Lattice Boltzmann method of nanoscale thermal behavior inside MOSFET and SOI-MOSFET

In recent years, the world has witnessed a huge technological revolution in terms of manufacturing electronic devices and reducing their size, which has reached nanoscale. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one of these devices. However, with its downsizing, it affects the efficiency of its associated devices due to the generated heat. In this paper, two-dimensional heat transfer inside a Silicon on Insulator (SOI) MOSFET and traditional MOS transistor is investigated using the Lattice Boltzmann Method (LBM) . It was found that the temperature reaches 340 K and 332 K for SOI-MOSFET and MOSFET at a Knudsen number (Kn=Λ/Lc) of 10, respectively, while the heat flux reaches 21.5 × 1011 W/m2 for SOI transistor and 18.7 × 1011 W/m2for MOS device. The insulating layer (SiO2)in the SOI transistor restrains heat release in the channel region. So, the conventional MOSFET at Kn =10 is thermally more stable, compared to SOI-MOSFET.

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-channel Eδ DC MOS Transistor

A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness (LER/LWR) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design (TCAD) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied with respect to different LER parameters, aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.

Novel pH Sensor Based on out-of-Equilibrium Body Potential Monitored in Silicon on Insulator with Metal Contacts

In the field of bio-chemical sensors, the ISFETs (Ion Sensing Field Effect Transistors) occupy an important position since 1972 [1]. ISFETs are based on the conductivity modulation when charges are placed close to the conductive channel or on the gate of the transistor. The majority of chemical and biochemical FET sensors monitor a change in the device current at constant gate voltage (VG) or a threshold voltage (VT) shift [2]. In both cases, the device is considered to be in a static state and its electrical response in “quasi-equilibrium”, even though the bio-chemical environment is modified in real-time. The originality of our work is to demonstrate the possibility of detection based on a measurement in out-of-equilibrium state of the device. Such out-of-equilibrium phenomena were already studied in silicon on insulator (SOI) devices and their presence is due to the fact that the body of the transistor is floating. When sweeping fast the device from accumulation to inversion or vice-versa, an SOI transistor shows an out-of-equilibrium body potential [3], which was exploited for memory applications [3]. The same phenomenon was shown in SOI substrates measured with metallic probes placed on the top silicon film and in which the substrate is used as back gate; DNA detection in this configuration was successfully demonstrated in [4].This paper shows the possibility to detect pH with a simple fabricated SOI structure with metal contacts deposited on the top, using the out-of-equilibrium body potential measurement. The out-of-equilibrium body potential (VB) is related to the absence of carriers in the Si film, while the VG is swept [5]. When the carriers are injected, the device reaches an equilibrium state and VB sharply drops to the “static” value. Interestingly, VB appears for low absolute gate-voltage values in which the current through the device is almost zero. Additionally, the out-of-equilibrium region is related to the VT value of the device, which is modulated by the presence of charges on the top Si, as in an ISFET. Hence the return to equilibrium will occur for different VG values, depending on the quantity of charges to-be-detected.Square mesas were etched on SOI wafers with 70nm silicon thickness and 30nm buried oxide (BOX) thickness. A lithography step allowed to define contact areas, where, the native silicon oxide was removed and a 300nm chromium (Cr) layer was deposited by sputtering at 120oC. The contact patterns were revealed after a lift-off step.The devices used for this study have two Cr pads on the edges (Fig.a). The pads were used as source (grounded) and as drain (for current measurement) or body contact. For the detection, a PDMS chamber with a 3mm diameter opening was placed in the center of each device. Initially, a reference curve without any solution was traced. Then the chamber was filled with solutions of pH values of 4, 7 or 10. The potential of the liquid was set to zero volts with an Ag/AgCl pseudo-reference electrode (RE), inserted through the upper limit of the liquid in the pH solution.Figure b and c show the drain current ID and the out-of-equilibrium VB versus VG of the samples under test when the solution was in contact with their top surface. Figure d illustrates the VT values extracted from the ID-VG curves and the VG values when VB=0.5V during the sharp drop. The results indicate a VB shift with various pH values. VB shift seems to be stronger than VT probably because it is traced when the device is depleted and hence the free carriers have an exponential dependence on the voltage. Additionally, the strong VB response occurs for low VG values (under the threshold), in a region where ID is small and more difficult to measure. This promises a more power-efficient detection method (VB based) compared to the commonly used modulation of conductance or VT shift. Explanation of the phenomena involved and more experimental results including a benchmark with wafers with thinner Si will be presented in the conference.In conclusion, devices based on SOI with Cr contacts are promising candidates for detection based on the out-of-equilibrium body potential reading. The dynamic reading method provides a robust voltage signature for lower operation voltages compared to the presently used “static” current measurements. The preliminary results imply a more pronounced shift to the presence of charges. In addition, the studied devices, which require very few and low temperature process steps, provide a naturally large sensing area, ideal for direct placement of charged species. Finally, the proximity of the charges to the conductive channel enhances the sensitivity of the devices.

Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron

Abstract:Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Radio Frequency (RF) Silicon-on-Insulator (SOI) is today a mainstream technology for several front-end module integrated circuits. The high quality of the trap-rich SOI substrate in terms of low insertion loss and high linearity is at the origin of its commercial success. Partially depleted SOI transistors characterized with a channel length from 180 nm down to 45 nm are currently manufactured on top of the trap-rich substrate. However, there is a growing interest for moving from partially to fully depleted SOI transistors in order to improve the RF and millimeter-waves performance of the transistor at low power consumption. On-going research explores the possibility of combining the best of the digital FD SOI devices and high quality RF SOI substrate to design low power mixed-mode communication system-on-chip.

Investigation and Comparison of the DIBL Parameter and Thermal Effects of SOD Transistors and SOI Transistors and Improving Them with the Change of Their BOX Thicknesses

In this paper, thermal effects and Drain Induced barrier lowering (DIBL) of silicon-on-insulator (SOI) and silicon-on-diamond (SOD) transistors with 22 nm channel lengths using hydrodynamic simulations have been investigated. Thermal conductivity of diamond in contrast to thermal conductivity of silicon dioxide is significantly higher. Hence, the heat transfers faster in silicon-on-diamond transistors. Lattice temperature of SODs is lower than that of similar SOIs. By using SODs in Integrated circuits with the first transistor turning on and active, neighboring transistors will have the same level of heat as the active transistor. As a result, the DIBL factor will be increased; this is an undesired phenomenon in CMOS applications. To resolve this issue, we propose a new method which is the thickness reduction of buried diamond layers inside of transistors. Due to this change, DIBL of active transistor will be improved, the exceeding lattice heat of side transistors will be evacuated through the devices and their temperatures will be deduced in large scale.

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

Compact On-Wafer Test Structures for Device RF Characterization

The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50- $\mu \text{m}$ -pitch RF probes. It is shown that by using these new test structures, the layoutgeometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100– $150~\mu \text{m}$ -pitch RF probes. 50- $\mu \text{m}$ -pitch de-embedding structures have been implemented on 0.18- $\mu \text{m}$ RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

Enhanced Radiation Hardness in SOI MOSFET with Embedded Tunnel Diode Layer

This paper presents an improved body tie structure for partially depleted silicon-on-insulator (SOI) MOSFETs. Inspired by tunneling current of degenerated p-n-junction at low forward bias, a tunnel diode layer is inserted at back channel forming a new type of body tie. The tunnel diode layer can be prepared either by ion implantation or in situ silicon deposition, which is fully compatible with present commercial SOI processes. The introduced body contact serves as an additional current flowing path for accumulated majority carriers generated by impact ionization or heavy-ion radiation, reducing critical floating body effects. The heavily doped tunnel diode layer extending from source to drain improves total dose radiation hardness and suppresses front-back channel coupling of SOI MOSFET for increasing back-gate threshold voltage and reduced width of space charge region. Experimental and simulation results validate the usefulness of the introduced body tie in enhancing radiation hardness of SOI transistor comparing with the conventional floating body devices. Therefore, SOI device with embedded tunnel diode layer can be considered as a promising candidate in spaceborne applications.

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

Radiation hardening technology in SOI materials and devices

Based on the great success of silicon material and silicon integrated circuit, the silicon-on-insulator (SOI) technology occurs as a new technology with unique advantages to break the limitation of traditional bulk silicon technology. The existence of the buried oxide (BOX) can fundamentally eliminate the latch-up effect of the bulk CMOS technology. The sensitive volume of charge collection in SOI device is smaller than in bulk one, potentially making SOI devices much more hardened to dose rate effect and single-event upset, the upset cross section is nearly two orders of magnitude smaller. These inherent advantages of SOI technology make it very important in military and space applications. However, the existence of the thick buried oxide also makes the total ionizing dose (TID) effect of the SOI devices more complicated. The radiation-induced trapped charge in the buried oxide can lead to serious degradations of the SOI devices and circuits in the space and nuclear radiation environment, such as the increases of the off-state leakage current in the partially-depleted devices and the decreases of the front-gate threshold voltage in the fully-depleted NMOS devices. Meanwhile, the relatively thick field oxide is also very soft to ionizing radiation. Two common types of field oxide isolation are local oxidation of silicon (LOCOS) and shallow trench isolation (STI). LOCOS isolation has been replaced by STI to reduce spacing between adjacent devices in the advanced submicron technology node. STI induced leakage after TID radiation has become a dramatic problem in modern technologies. Both the STI oxide and the buried oxide can potentially impact the total dose tolerance in SOI transistors. This limits the application of SOI technology in radiation hardening. It is only by solving the problem of the total dose hardening that the SOI technology can better fulfill its military applications. In addition, the single-event effect and dose rate effect of the SOI circuits become more complicated due to the less critical charge for upset, higher operating frequency and enhanced parasitic bipolar effect for the deep submicron technology. All these factors challenge the hardening design technique of the SOI devices and circuits. In this paper, the difference of ionizing radiation effects between bulk-silicon devices and SOI devices is compared. In order to enhance the radiation hardness of single event effect and dose rate effect in SOI device, the method of suppressing the parasitic bipolar transistor effect is proposed. Furthermore, the radiation hardened methods for TID effect in SOI technology is investigated from two levels: radiation hardened by material and process, radiation hardened by layout. The development of an independent SOI radiation hardening technology will contribute to solve the problem in military electronics, such as radiation hardening, high reliability, and to promote the sustainable development of national defense construction and national security.

Development of radiation hard CMOS active pixel sensors for HL-LHC

New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

Radiation hardness of a 180 nm SOI monolithic active pixel sensor

The use of Silicon-on-Insulator (SOI) technology as a particle detector in a high radiation environment is, at present, limited mostly by radiation effects on the transistor characteristics, back gate effect, and mutual coupling between the Buried Oxide (BOX) and the sensor. We have fabricated and tested a new 0.18μm SOI CMOS monolithic pixel sensor using the XFAB process. In contrast to the most commonly used SOI technologies, this particular technology uses partially depleted SOI transistors, offering a double well structure, which shields the thin gate oxide transistors from the BOX. In addition, an increased distance between transistors and a thicker BOX than has been previously used offers promising solutions to the performance limitations mentioned above. The process further allows the use of high voltages (up to 200V), which are used to partially deplete the substrate. Thus, the newly fabricated device in the XFAB process is especially interesting for applications in extremely high radiation environments, such as LHC experiments. A four stage validation programme of the technology and the fabricated monolithic pixel sensor has been performed and its results are shown in this paper. The first targets radiation hardness of the transistor characteristics up to 700Mrad, the second investigates the existence of the back gate effect, the third one targets the coupling between the BOX and the sensor, and the fourth investigates the characterization of charge collection in the sensor diode below the BOX.

Thermal Transport in Hotspots Using the Lattice Boltzmann Method with Application to Silicon-on-Insulator Transistors

Silicon-on-insulator (SOI) transistors have been widely used in the micro-electronic devices. The Lattice Boltzmann method (LBM) is employed to simulate the heat conductions of hotspots appeared in a SOI transistor. The results show that a thermal wave effect is appeared in micro-region, and it can not be found in Fourier prediction. Comparing the results obtained by the Fourier law and LBM, we find that the LBM solution shows approximately 22% higher energy density than the Fourier prediction. When two thermal waves form different hotspots meet together, a significant energy enhancement will be appeared.

Enhanced Radiation Sensitivity in Short-Channel Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors

The total ionizing dose effects of partially depleted silicon-on-insulator (SOI) transistors in a 0.13 μm technology are studied by 60Co γ-ray irradiation. Radiation enhanced drain-induced barrier lowering (DIBL) under different bias conditions is related to the parasitic bipolar in the SOI transistor and oxide trapped charge in the buried oxide, and it is experimentally observed for short channel transistors. The enhanced DIBL effect manifests as the DIBL parameter increases with total dose. Body doping concentration is a key factor affecting the total ionizing dose effect of the transistor. The low body doping transistor exhibits not only significant front gate threshold voltage shift as a result of the coupling effect, but also great off-state leakage at high drain voltage due to the enhanced DIBL effect.