Compact On-Wafer Test Structures for Device RF Characterization

Abstract

The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50- $\mu \text{m}$ -pitch RF probes. It is shown that by using these new test structures, the layoutgeometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100– $150~\mu \text{m}$ -pitch RF probes. 50- $\mu \text{m}$ -pitch de-embedding structures have been implemented on 0.18- $\mu \text{m}$ RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions.